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MC74AC194D PDF预览

MC74AC194D

更新时间: 2024-10-31 22:38:55
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 移位寄存器
页数 文件大小 规格书
7页 217K
描述
4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTER

MC74AC194D 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:PLASTIC, SOIC-16Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.91
其他特性:HOLD MODE计数方向:BIDIRECTIONAL
系列:ACJESD-30 代码:R-PDSO-G16
JESD-609代码:e0长度:9.9 mm
负载电容(CL):50 pF逻辑集成电路类型:PARALLEL IN PARALLEL OUT
最大频率@ Nom-Sup:115000000 Hz位数:4
功能数量:1端子数量:16
最高工作温度:85 °C最低工作温度:-40 °C
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP16,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:3.3/5 V
传播延迟(tpd):14 ns认证状态:Not Qualified
座面最大高度:1.75 mm子类别:Shift Registers
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:POSITIVE EDGE
宽度:3.9 mm最小 fmax:150 MHz
Base Number Matches:1

MC74AC194D 数据手册

 浏览型号MC74AC194D的Datasheet PDF文件第2页浏览型号MC74AC194D的Datasheet PDF文件第3页浏览型号MC74AC194D的Datasheet PDF文件第4页浏览型号MC74AC194D的Datasheet PDF文件第5页浏览型号MC74AC194D的Datasheet PDF文件第6页浏览型号MC74AC194D的Datasheet PDF文件第7页 
4-BIT BIDIRECTIONAL  
UNIVERSAL SHIFT  
REGISTER  
The MC74AC194/74ACT194 is a high-speed 4-bit bidirectional universal shift  
register. As a high-speed multifunctional, sequential building block, it is useful in  
a wide variety of applications. It may be used in serial-serial, shift left, shift right,  
serial-parallel, parallel-serial, and parallel-parallel data register transfers. The  
AC/ACT194 is similar in operation to the AS195 universal shift register, with  
added features of shift left without external connections and hold (do nothing)  
modes of operation.  
Typical Shift Frequency of 150 MHz  
Asynchronous Master Reset  
Hold (Do Nothing) Mode  
Fully Synchronous Serial or Parallel Data Transfers  
N SUFFIX  
CASE 648-08  
PLASTIC  
FUNCTIONAL DESCRIPTION  
The MC74AC/74ACT194 contains four edge-triggered D flip-flops and the  
necessary interstage logic to synchronously perform shift right, shift left, parallel  
load and hold operations. Signals applied to the Select (S , S ) inputs  
0
1
determine the type of operation, as shown in the Mode Select Table. Signals  
on the Select, Parallel data (P –P ) and Serial data (D , D ) inputs can  
change when the clock is in either state, provided only that the recommended  
setup and hold times, with respect to the clock rising edge, are observed. A  
LOW signal on Master Reset (MR) overrides all other inputs and forces the  
outputs LOW.  
0
3
SR SL  
D SUFFIX  
CASE 751B-05  
PLASTIC  
MODE SELECT TABLE  
V
1
2
3
4
5
6
7
8
16  
15  
14  
13  
MR  
CC  
Inputs  
Outputs  
Operating  
Mode  
D
Q
SR  
0
1
MR  
L
S
S
D
D
P
Q
Q
Q
Q
1
0
SR  
X
SL  
n
0
1
2
3
Reset  
Hold  
X
X
X
X
X
L
L
L
L
P
Q
0
H
l
l
X
X
q
0
q
1
q
2
q
3
P
Q
1
2
H
H
h
h
l
l
X
X
l
X
X
q
1
q
1
q
2
q
2
q
3
q
3
L
Shift Left  
h
H
12  
11  
10  
9
P
Q
2
3
H
H
l
l
h
h
l
X
X
X
X
L
q
0
q
0
q
1
q
1
q
2
2
Shift Right  
h
H
q
P
CP  
3
Parallel Load  
H
h
h
X
X
p
p
0
p
1
p
2
p
3
n
S
1
l = LOW voltage level one setup time prior to the LOW-to-HIGH clock transition.  
h = HIGH voltage level one setup time prior to the LOW-to-HIGH clock transition.  
D
SL  
S
P
(q ) = Lower case letters indicate the state of the referenced input (or output) one setup  
0
n
n
GND  
time prior to the LOW-to-HIGH clock transition.  
H = HIGH Voltage Level  
L = LOW Voltage Level  
X = Immaterial  
2
3
4
5
6
7
D
P
P
P
P D  
SR  
0
1
2 3 SL  
S
9
0
S
10  
11  
1
CP  
MR  
1
Q
Q
Q
Q
0
1
2 3  
15 14 13 12  
FACT DATA  
5-1  

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