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MC56F80726VLF PDF预览

MC56F80726VLF

更新时间： 2024-09-16 15:18:31
品牌 Logo 应用领域
恩智浦 - NXP /
页数 文件大小 规格书
71页 1045K
描述
32-bit DSC, 56800EF core, 32KB Flash, 100MHz, LQFP48

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MC56F80726VLF 数据手册

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Document Number MC56F80XXX  
Rev. 2.1, 02/2023  
NXP Semiconductors  
Data Sheet: Technical Data  
MC56F80XXX  
MC56F80xxx  
Supports MC56F807xx and  
MC56F806xx  
Features  
• One high-resolution eFlexPWM module, with up to 12  
PWM outputs, including up to 8 channels with 312ps  
resolution NanoEdge placement  
• This family of digital signal controllers (DSCs) is  
based on the 32-bit 56800EF core. On a single chip,  
each device combines the processing power of a DSP  
and the functionality of an MCU, with a flexible set of  
peripherals to support many target applications:  
– Industrial control  
• Communication interfaces  
– Up to two high-speed queued SCI (QSCI) modules  
with LIN slave functionality  
– One queued SPI (QSPI) module  
– Motion control  
– One LPI2C module (supports Full PMBus)  
– Home appliances  
– General-purpose inverters  
• Timers  
– One 16-bit quad timer (1 x 4Ch)  
– Up to three 32-bit Periodic Interval Timers (PITs)  
– One enhanced Quadrature Decoder (eQDC)  
– Smart sensors, fire and security systems  
– Switched-mode power supply and power  
management  
– Uninterruptible power supplies (UPS)  
– Solar inverter  
– Medical monitoring applications  
• Security and integrity  
– Cyclic Redundancy Check (CRC) generator  
– Windowed Computer operating properly (COP)  
watchdog  
• DSC based on 32-bit 56800EF core  
– Up to 100 MIPS at 100 MHz core frequency  
– DSP and MCU functionality in a unified, C-efficient  
architecture  
– External Watchdog Monitor (EWM)  
• Clocks  
– On-chip oscillators: 200 kHz, and 8/2MHz IRC  
– Crystal / resonator oscillator  
– Enhanced single-precision Floating Point math Unit  
(eFPU)  
– COordinate Rotation DIgital Compute (CORDIC)  
engine  
• System  
– 4-channel enhanced DMA controller, supporting up  
to 63 request sources  
• On-chip memory  
– Integrated power-on reset (POR) and low-voltage  
interrupt (LVI) and brown-out reset module  
– Inter-Module Crossbar and Event Generator  
– JTAG/enhanced on-chip emulation (EOnCE) for  
unobtrusive, real-time debugging  
– Up to 64 KB flash memory  
– 8 KB data/program RAM  
– Both on-chip flash memory and RAM can be  
mapped into both program and data memory spaces  
• Analog  
• Operating characteristics  
– Two high-speed, 12-bit ADCs with dynamic x1, x2,  
and x4 programmable amplifier  
– Up to two operational amplifiers, programmable  
gain up to x16  
– Three analog comparators with integrated 8-bit DAC  
references  
– Single supply: 2.7 V to 3.6 V  
– Operation ambient temperature (V grade  
temperature): -40℃ to 105℃  
– Operation ambient temperature (M grade  
temperature): -40℃ to 125℃  
• 64-pin LQFP, 48-pin LQFP packages (32-pin LQFP  
and QFN optional)  
– On-chip temperature sensors  
NXP reserves the right to change the production detail specifications as may be  
required to permit improvements in the design of its products.  
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