Datasheet > MC54HC174A

MC54HC174A

更新时间： 2024-10-14 04:40:47

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		触发器栅时钟
页数	文件大小	规格书
6页	206K
描述
Hex D Flip-Flop With Common Clock And Reset High-Performance Silicon-Gate CMOS

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MC54HC174A 数据手册

SEMICONDUCTOR TECHNICAL DATA

High–Performance Silicon–Gate CMOS

J SUFFIX

CERAMIC PACKAGE

CASE 620–10

The MC54/74HC174A is identical in pinout to the LS174. The device

inputs are compatible with standard CMOS outputs; with pullup resistors,

they are compatible with LSTTL outputs.

This device consists of six D flip–flops with common Clock and Reset

inputs. Each flip–flop is loaded with a low–to–high transition of the Clock

input. Reset is asynchronous and active–low.

N SUFFIX

PLASTIC PACKAGE

CASE 648–08

•

Output Drive Capability: 10 LSTTL Loads

TTL NMOS Compatible Input Levels

Outputs Directly Interface to CMOS, NMOS, and TTL

Operating Voltage Range: 4.5 to 5.5 V

Low Input Current: 1.0 µA

D SUFFIX

SOIC PACKAGE

CASE 751B–05

In Compliance with the Requirements Defined by JEDEC Standard

No. 7A

•

Chip Complexity: 162 FETs or 40.5 Equivalent Gates

ORDERING INFORMATION

MC54HCXXXAJ

MC74HCXXXAN

MC74HCXXXAD

Ceramic

Plastic

SOIC

LOGIC DIAGRAM

DATA

INPUTS

NONINVERTING

OUTPUTS

PIN ASSIGNMENT

RESET

CLOCK

RESET

PIN 16 = V

PIN 8 = GND

GND

CLOCK

Design Criteria

Value

40.5

1.5

Units

ea.

Internal Gate Count*

FUNCTION TABLE

Internal Gate Propagation Delay

Internal Gate Power Dissipation

Speed Power Product

Inputs

Reset Clock

Output

5.0

µW

.0075

* Equivalent to a two–input NAND gate.

No Change

10/95

REV 6

Motorola, Inc. 1995

12 3 4 5 6

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