MC54HC175

更新时间： 2024-10-14 00:01:07

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		触发器时钟
页数	文件大小	规格书
8页	103K
描述
Quad D Flip-Flop with Common Clock and Reset

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数据手册

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MC54HC175 数据手册

SEMICONDUCTOR TECHNICAL DATA

High–Performance Silicon–Gate CMOS

J SUFFIX

CERAMIC PACKAGE

CASE 620–10

The MC54/74HC175 is identical in pinout to the LS175. The device inputs

are compatible with standard CMOS outputs; with pullup resistors, they are

compatible with LSTTL outputs.

This device consists of four D flip–flops with common Reset and Clock

inputs, and separate D inputs. Reset (active–low) is asynchronous and

occurs when a low level is applied to the Reset input. Information at a D input

is transferred to the corresponding Q output on the next positive going edge

of the Clock input.

N SUFFIX

PLASTIC PACKAGE

CASE 648–08

•

Output Drive Capability: 10 LSTTL Loads

Outputs Directly Interface to CMOS, NMOS, and TTL

Operating Voltage Range: 2 to 6 V

D SUFFIX

SOIC PACKAGE

CASE 751B–05

Low Input Current: 1 µA

High Noise Immunity Characteristic of CMOS Devices

In Compliance with the Requirements Defined by JEDEC Standard

No. 7A

ORDERING INFORMATION

MC54HCXXXJ

MC74HCXXXN

MC74HCXXXD

Ceramic

Plastic

SOIC

•

Chip Complexity 166 FETs or 41.5 Equivalent Gates

LOGIC DIAGRAM

CLOCK

PIN ASSIGNMENT

RESET

INVERTING

AND

NONINVERTING

OUTPUTS

DATA

INPUTS

RESET

PIN 16 = V

PIN 8 = GND

GND

CLOCK

FUNCTION TABLE

Inputs

Reset Clock

Outputs

No Change

10/95

Motorola, Inc. 1995

REV 6

12 3 4 5 6 7 8

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与MC54HC175相关器件

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MC54HC175J	MOTOROLA	获取价格	Quad D Flip-Flop with Common Clock and Reset
MC54HC175JD	MOTOROLA	获取价格	暂无描述
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