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MC54HC240AJD PDF预览

MC54HC240AJD

更新时间: 2024-11-14 13:11:15
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 驱动器
页数 文件大小 规格书
8页 110K
描述
HC/UH SERIES, DUAL 4-BIT DRIVER, INVERTED OUTPUT, CDIP20, CERAMIC, DIP-20

MC54HC240AJD 技术参数

是否无铅:含铅是否Rohs认证:不符合
生命周期:Obsolete零件包装代码:DIP
包装说明:DIP,针数:20
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.27Is Samacsys:N
系列:HC/UHJESD-30 代码:R-CDIP-T20
JESD-609代码:e0长度:24.515 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
位数:4功能数量:2
端口数量:2端子数量:20
最高工作温度:125 °C最低工作温度:-55 °C
输出特性:3-STATE输出极性:INVERTED
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:DIP
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED传播延迟(tpd):24 ns
认证状态:Not Qualified座面最大高度:5.08 mm
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:MILITARY
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.62 mm
Base Number Matches:1

MC54HC240AJD 数据手册

 浏览型号MC54HC240AJD的Datasheet PDF文件第2页浏览型号MC54HC240AJD的Datasheet PDF文件第3页浏览型号MC54HC240AJD的Datasheet PDF文件第4页浏览型号MC54HC240AJD的Datasheet PDF文件第5页浏览型号MC54HC240AJD的Datasheet PDF文件第6页浏览型号MC54HC240AJD的Datasheet PDF文件第7页 
SEMICONDUCTOR TECHNICAL DATA  
High–Performance Silicon–Gate CMOS  
J SUFFIX  
CERAMIC PACKAGE  
CASE 732–03  
20  
20  
The MC54/74HC240A is identical in pinout to the LS240. The device  
inputs are compatible with standard CMOS outputs; with pullup resistors,  
they are compatible with LSTTL outputs.  
This octal noninverting buffer/line driver/line receiver is designed to be  
used with 3–state memory address drivers, clock drivers, and other  
sub–oriented systems. The device has inverting outputs and two active–low  
output enables.  
1
N SUFFIX  
PLASTIC PACKAGE  
CASE 738–03  
1
The HC240A is similar in function to the HC241A and HC244A.  
DW SUFFIX  
SOIC PACKAGE  
CASE 751D–04  
Output Drive Capability: 15 LSTTL Loads  
Outputs Directly Interface to CMOS, NMOS, and TTL  
Operating Voltage Range: 2 to 6 V  
20  
1
1
DT SUFFIX  
TSSOP PACKAGE  
CASE 948E–02  
Low Input Current: 1 µA  
20  
High Noise Immunity Characteristic of CMOS Devices  
In Compliance with the Requirements Defined by JEDEC Standard  
No. 7A  
ORDERING INFORMATION  
Chip Complexity: 120 FETs or 30 Equivalent Gates  
MC54HCXXXAJ  
MC74HCXXXAN  
MC74HCXXXADW  
MC74HCXXXADT  
Ceramic  
Plastic  
SOIC  
TSSOP  
LOGIC DIAGRAM  
2
18  
A1  
YA1  
PIN ASSIGNMENT  
4
6
8
16  
14  
12  
ENABLE A  
1
20  
V
CC  
A2  
A3  
A4  
YA2  
YA3  
YA4  
A1  
YB4  
A2  
2
3
4
19  
18  
17  
ENABLE B  
YA1  
B4  
YB3  
A3  
5
16  
15  
14  
13  
12  
11  
YA2  
B3  
DATA  
INPUTS  
INVERTING  
OUTPUTS  
11  
13  
15  
17  
9
7
5
3
6
B1  
B2  
B3  
B4  
YB1  
YB2  
YB3  
YB4  
YB2  
A4  
7
YA3  
B2  
8
YB1  
GND  
9
YA4  
B1  
10  
FUNCTION TABLE  
PIN 20 = V  
CC  
PIN 10 = GND  
1
ENABLE A  
ENABLE B  
OUTPUT  
ENABLES  
Inputs  
Enable A,  
Enable B A, B  
Outputs  
19  
YA, YB  
L
L
H
L
H
X
H
L
Z
Z = high impedance  
2/97  
Motorola, Inc. 1997  
REV 7  

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