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MC34C86D PDF预览

MC34C86D

更新时间: 2024-09-12 22:39:59
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA /
页数 文件大小 规格书
4页 116K
描述
Quad EIA-422-A Line Receiver

MC34C86D 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:SOP, SOP16,.4Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.89输入特性:DIFFERENTIAL SCHMITT TRIGGER
接口集成电路类型:LINE RECEIVER接口标准:EIA-422-A
JESD-30 代码:R-PDSO-G16JESD-609代码:e0
长度:9.9 mm功能数量:2
端子数量:16最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
最大输出低电流:0.006 A输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP16,.4封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V认证状态:Not Qualified
最大接收延迟:30 ns接收器位数:2
座面最大高度:1.75 mm子类别:Line Driver or Receivers
最大压摆率:12 mA最大供电电压:5.5 V
最小供电电压:4.5 V标称供电电压:5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:3.9 mmBase Number Matches:1

MC34C86D 数据手册

 浏览型号MC34C86D的Datasheet PDF文件第2页浏览型号MC34C86D的Datasheet PDF文件第3页浏览型号MC34C86D的Datasheet PDF文件第4页 
Order this document  
by MC34C86/D  
SEMICONDUCTOR TECHNICAL DATA  
Product Preview  
P SUFFIX  
PLASTIC DIP  
CASE 648  
CMOS  
16  
The MC34C86 is a quad differential line receiver designed for digital data  
transmission over balanced lines. The MC34C86 meets all the requirements of  
standard EIA–422–A while retaining the low–power characteristics of CMOS.  
The MC34C86 has an input sensitivity of 200 mV over the common mode  
input voltage range of ± 7 V. In addition, each receiver chain has internal  
hysteresis circuitry to improve noise margin and discourage output instability for  
slowly changing input waveforms.  
1
D SUFFIX  
SOG PACKAGE  
CASE 751B  
16  
1
The MC34C86 is pin compatible with the MC3486.  
All pins are protected against damage due to electrostatic discharges.  
ORDERING INFORMATION  
MC34C86P  
MC34C86D  
Plastic DIP  
SOG Package  
Typical Power Supply Current: 6 mA  
2000 V ESD Protection on the Inputs and Outputs  
Typical Propagation Delay: 18 ns  
Typical Input Hysteresis: 75 mV  
Meets the Requirements of Standard EIA–422–A  
Operation from Single 5 V Supply  
High Impedance Mode for Outputs Connected to System Buses  
TTL/CMOS Compatible Outputs  
BLOCK DIAGRAM  
B/D  
INPUT INPUT  
INPUT INPUT  
INPUT INPUT  
INPUT INPUT  
A/C  
CONTROL  
D2  
D1  
B2  
B1  
C2  
C1  
A2  
A1  
CONTROL  
12  
4
10  
9
14 15  
6
7
2
1
+
+
+
+
8
GND  
16  
11  
13  
5
3
V
OUTPUT  
D
OUTPUT  
B
OUTPUT  
C
OUTPUT  
A
CC  
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.  
REV 4  
10/95  
Motorola, Inc. 1995  

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