Datasheet > MC1670L

MC1670L

更新时间： 2024-09-09 22:51:27

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		触发器
页数	文件大小	规格书
4页	80K
描述
Master-Slave Flip-Flop

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中文翻译

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数据手册

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MC1670L 数据手册

SEMICONDUCTOR TECHNICAL DATA

Master slave construction renders the MC1670 relatively insensitive to the

shape of the clock waveform, since only the voltage levels at the clock inputs

control the transfer of information from data input (D) to output.

When both clock inputs (C1 and C2) are in the low state, the data input

affects only the “Master” portion of the flip-flop. The data present in the “Master”

is transferred to the “Slave” when clock inputs (C1 “OR” C2) are taken from a

low to a high level. In other words, the output state of the flip-flop changes on the

positive transition of the clock pulse.

While either C1 “OR” C2 is in the high state, the “Master” (and data input) is

disabled.

L SUFFIX

CERAMIC PACKAGE

CASE 620–10

Asynchronous Set (S) and Reset (R) override Clock (C) and Data (D) inputs.

Power Dissipation = 220 mW typ (No Load)

= 350 MHz typ

Tog

TRUTH TABLE

n+1

N.D.

LOGIC DIAGRAM

ND = Not Defined

C = C1 + C2

= Pin 1

= Pin 16

= Pin 8

CC1

CC2

ELECTRICAL CHARACTERISTICS

–30°C

+25°C

+85°C

Characteristic

Symbol Min Max Min Max Min Max Unit

Power Supply Drain Current

—

mAdc

Input Current

Set, Reset

Clock

µAdc

inH

PIN ASSIGNMENT

—

550

250

270

—

Data

CC2

CC1

Switching Times

Propagation Delay

1.0

0.9

0.5

2.7

2.1

1.1

1.0

0.6

2.5

1.9

1.1

1.0

0.6

2.9

2.3

Rise Time (10% to 90%)

Fall Time (10% to 90%)

Setup Time

–

RESET

SET

—

0.4

0.5

—

S“1”

S“0”

Hold Time

—

0.3

0.5

—

DATA

H“1”

H“0”

CLOCK 1

Toggle Frequency

270

—

300

—

270

—

MHz

Tog

CLOCK 2

3/93

REV 5

4–356

Motorola, Inc. 1996

12 3 4

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