SEMICONDUCTOR TECHNICAL DATA
L SUFFIX
CERAMIC
CASE 620
The MC14532B is constructed with complementary MOS (CMOS)
enhancement mode devices. The primary function of a priority encoder is to
provide a binary address for the active input with the highest priority. Eight
data inputs (D0 thru D7) and an enable input (E are provided. Five outputs
in)
are available, three are address outputs (Q0 thru Q2), one group select (GS)
P SUFFIX
PLASTIC
CASE 648
and one enable output (E ).
out
•
•
•
Diode Protection on All Inputs
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two Low–power TTL Loads or One Low–Power
Schottky TTL Load over the Rated Temperature Range
D SUFFIX
SOIC
CASE 751B
MAXIMUM RATINGS* (Voltages Referenced to V
)
SS
Symbol
Parameter
DC Supply Voltage
Value
Unit
V
ORDERING INFORMATION
V
DD
– 0.5 to + 18.0
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
Plastic
Ceramic
SOIC
V , V
Input or Output Voltage (DC or Transient)
– 0.5 to V
DD
+ 0.5
V
in out
I , I
Input or Output Current (DC or Transient),
per Pin
± 10
mA
in out
T
A
= – 55° to 125°C for all packages.
P
Power Dissipation, per Package†
Storage Temperature
500
mW
C
D
T
stg
– 65 to + 150
260
PIN ASSIGNMENT
T
Lead Temperature (8–Second Soldering)
C
L
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
D4
D5
D6
D7
1
2
16
15
V
DD
E
out
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C
Ceramic “L” Packages: – 12 mW/ C From 100 C To 125 C
3
4
5
6
7
8
14
13
12
11
10
9
GS
D3
D2
D1
D0
Q0
TRUTH TABLE
E
in
Input
Output
Q2
E
in
D7 D6 D5 D4 D3 D2 D1 D0 GS Q2 Q1 Q0
E
out
Q1
SS
0
1
X
0
X
0
X
0
X
0
X
0
X
0
X
0
X
0
0
0
0
0
0
0
0
0
0
1
V
1
1
1
1
1
0
0
0
X
1
0
0
X
X
1
0
X
X
X
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
1
1
1
1
1
1
1
1
1
0
0
1
0
1
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
X
1
0
0
X
X
1
0
X
X
X
1
1
1
1
1
0
0
0
0
1
1
0
0
1
0
1
0
0
0
0
0
X = Don’t Care
This device contains protection circuitry to guard against damage
due to high static voltages or electric fields. However, precautions must
be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, V and
in
V
out
should be constrained to the range V
SS
≤ (V or V ) ≤ V .
in out DD
Unused inputs must always be tied to an appropriate logic voltage
level (e.g., either V or V ). Unused outputs must be left open.
SS DD
REV 3
1/94
Motorola, Inc. 1995
MOTOROLA CMOS LOGIC DATA
MC14532B
1