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MC14531BCLDS

更新时间： 2024-11-04 12:59:27
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摩托罗拉 - MOTOROLA /
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MC14531BCLDS 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
L SUFFIX  
CERAMIC  
CASE 620  
The MC14531B 12–bit parity tree is constructed with MOS P–channel and  
N–channel enhancement mode devices in a single monolithic structure. The  
circuit consists of 12 data–bit inputs (D0 thru D11), and even or odd parity  
selection input (W) and an output (Q). The parity selection input can be  
considered as an additional bit. Words of less than 13 bits can generate an  
even or odd parity output if the remaining inputs are selected to contain an  
even or odd number of ones, respectively. Words of greater than 12–bits can  
be accommodated by cascading other MC14531B devices by using the W  
input. Applications include checking or including a redundant (parity) bit to a  
word for error detection/correction systems, controller for remote digital  
sensors or switches (digital event detection/correction), or as a multiple input  
summer without carries.  
P SUFFIX  
PLASTIC  
CASE 648  
D SUFFIX  
SOIC  
CASE 751B  
•
•
•
Supply Voltage Range = 3.0 Vdc to 18 Vdc  
All Outputs Buffered  
Capable of Driving Two Low–Power TTL Loads or One Low–Power  
Schottky TTL Load Over the Rated Temperature Range  
Variable Word Length  
ORDERING INFORMATION  
MC14XXXBCP  
MC14XXXBCL  
MC14XXXBD  
Plastic  
Ceramic  
SOIC  
•
•
T
A
= – 55° to 125°C for all packages.  
Diode Protection on All Inputs  
MAXIMUM RATINGS* (Voltages Referenced to V  
)
SS  
Symbol  
Parameter  
DC Supply Voltage  
Value  
Unit  
V
V
DD  
– 0.5 to + 18.0  
V , V  
Input or Output Voltage (DC or Transient)  
– 0.5 to V  
DD  
+ 0.5  
V
in out  
I , I  
Input or Output Current (DC or Transient),  
per Pin  
± 10  
mA  
in out  
P
Power Dissipation, per Package†  
Storage Temperature  
500  
mW  
C
D
T
stg  
– 65 to + 150  
260  
T
Lead Temperature (8–Second Soldering)  
C
L
TRUTH TABLE  
* Maximum Ratings are those values beyond which damage to the device may occur.  
†Temperature Derating:  
Inputs  
Output  
Decimal  
(Octal)  
Equivalent  
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C  
Ceramic “L” Packages: – 12 mW/ C From 100 C To 125 C  
W
D11 D10  
…
D2  
D1  
D0  
Q*  
0
0
0
0
0
0
0
0
0
0
0
0
…
…
…
…
0
0
0
0
0
0
1
1
0
1
0
1
0
1
2
3
(0)  
(1)  
(2)  
(3)  
0
1
1
0
LOGIC DIAGRAM  
D0  
7
0
0
0
0
0
0
0
0
0
0
0
0
…
…
…
…
1
1
1
1
0
0
1
1
0
1
0
1
4
5
6
7
(4)  
(5)  
(6)  
(7)  
1
0
0
1
D1  
D2  
6
5
*
*
*
*
*
*
*
*
*
*
…
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
D3  
D4  
4
3
D5  
D6  
2
1
1
1
1
1
1
1
1
1
1.  
1
1
…
…
…
…
0
0
0
0
0
0
1
1
0
1
0
1
8184 (17770)  
8185 (17771)  
8186 (17772)  
8187 (17773)  
0
1
1
0
9
Q
D7 15  
D8 14  
1
1
1
1
1
1
1
1
1
1
1
1
1
…
…
…
…
1
1
1
1
0
0
1
1
0
1
0
1
8188 (17774)  
8189 (17775)  
8190 (17776)  
8191 (17777)  
1
0
0
1
D9 13  
D10 12  
V
V
= PIN 16  
= PIN 8  
DD  
SS  
D11 11  
*0 = Even Parity  
1 = Odd Parity  
NOTE:May redefine to suit application by manipulating W and/or other  
available D’s.  
ODD/EVEN W 10  
Q = D0  
D1  
D2  
D11  
W
REV 3  
1/94  
Motorola, Inc. 1995  
12345

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