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MC14531BCLD

更新时间： 2024-11-29 13:01:59
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA /
页数 文件大小 规格书
5页 175K
描述
4000/14000/40000 SERIES, 12-BIT PARITY GENERATOR/CHECKER, CONFIGURABLE OUTPUT, CDIP16, 620-09

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MC14531BCLD 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：DIP包装说明：DIP, DIP16,.3
针数：16Reach Compliance Code：unknown
HTS代码：8542.39.00.01风险等级：5.91
其他特性：ODD/EVEN PARITY GENERATOR系列：4000/14000/40000
JESD-30 代码：R-GDIP-T16JESD-609代码：e0
长度：19.3 mm负载电容（CL）：50 pF
逻辑集成电路类型：PARITY GENERATOR/CHECKER位数：12
功能数量：1端子数量：16
最高工作温度：85 °C最低工作温度：-40 °C
输出极性：CONFIGURABLE封装主体材料：CERAMIC, GLASS-SEALED
封装代码：DIP封装等效代码：DIP16,.3
封装形状：RECTANGULAR封装形式：IN-LINE
峰值回流温度（摄氏度）：NOT SPECIFIED电源：5/15 V
传播延迟（tpd）：1320 ns认证状态：Not Qualified
座面最大高度：4.19 mm子类别：Arithmetic Circuits
最大供电电压 (Vsup)：18 V最小供电电压 (Vsup)：3 V
标称供电电压 (Vsup)：5 V表面贴装：NO
技术：CMOS温度等级：INDUSTRIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：7.62 mm
Base Number Matches：1

MC14531BCLD 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
L SUFFIX  
CERAMIC  
CASE 620  
The MC14531B 12–bit parity tree is constructed with MOS P–channel and  
N–channel enhancement mode devices in a single monolithic structure. The  
circuit consists of 12 data–bit inputs (D0 thru D11), and even or odd parity  
selection input (W) and an output (Q). The parity selection input can be  
considered as an additional bit. Words of less than 13 bits can generate an  
even or odd parity output if the remaining inputs are selected to contain an  
even or odd number of ones, respectively. Words of greater than 12–bits can  
be accommodated by cascading other MC14531B devices by using the W  
input. Applications include checking or including a redundant (parity) bit to a  
word for error detection/correction systems, controller for remote digital  
sensors or switches (digital event detection/correction), or as a multiple input  
summer without carries.  
P SUFFIX  
PLASTIC  
CASE 648  
D SUFFIX  
SOIC  
CASE 751B  
•
•
•
Supply Voltage Range = 3.0 Vdc to 18 Vdc  
All Outputs Buffered  
Capable of Driving Two Low–Power TTL Loads or One Low–Power  
Schottky TTL Load Over the Rated Temperature Range  
Variable Word Length  
ORDERING INFORMATION  
MC14XXXBCP  
MC14XXXBCL  
MC14XXXBD  
Plastic  
Ceramic  
SOIC  
•
•
T
A
= – 55° to 125°C for all packages.  
Diode Protection on All Inputs  
MAXIMUM RATINGS* (Voltages Referenced to V  
)
SS  
Symbol  
Parameter  
DC Supply Voltage  
Value  
Unit  
V
V
DD  
– 0.5 to + 18.0  
V , V  
Input or Output Voltage (DC or Transient)  
– 0.5 to V  
DD  
+ 0.5  
V
in out  
I , I  
Input or Output Current (DC or Transient),  
per Pin  
± 10  
mA  
in out  
P
Power Dissipation, per Package†  
Storage Temperature  
500  
mW  
C
D
T
stg  
– 65 to + 150  
260  
T
Lead Temperature (8–Second Soldering)  
C
L
TRUTH TABLE  
* Maximum Ratings are those values beyond which damage to the device may occur.  
†Temperature Derating:  
Inputs  
Output  
Decimal  
(Octal)  
Equivalent  
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C  
Ceramic “L” Packages: – 12 mW/ C From 100 C To 125 C  
W
D11 D10  
…
D2  
D1  
D0  
Q*  
0
0
0
0
0
0
0
0
0
0
0
0
…
…
…
…
0
0
0
0
0
0
1
1
0
1
0
1
0
1
2
3
(0)  
(1)  
(2)  
(3)  
0
1
1
0
LOGIC DIAGRAM  
D0  
7
0
0
0
0
0
0
0
0
0
0
0
0
…
…
…
…
1
1
1
1
0
0
1
1
0
1
0
1
4
5
6
7
(4)  
(5)  
(6)  
(7)  
1
0
0
1
D1  
D2  
6
5
*
*
*
*
*
*
*
*
*
*
…
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
D3  
D4  
4
3
D5  
D6  
2
1
1
1
1
1
1
1
1
1
1.  
1
1
…
…
…
…
0
0
0
0
0
0
1
1
0
1
0
1
8184 (17770)  
8185 (17771)  
8186 (17772)  
8187 (17773)  
0
1
1
0
9
Q
D7 15  
D8 14  
1
1
1
1
1
1
1
1
1
1
1
1
1
…
…
…
…
1
1
1
1
0
0
1
1
0
1
0
1
8188 (17774)  
8189 (17775)  
8190 (17776)  
8191 (17777)  
1
0
0
1
D9 13  
D10 12  
V
V
= PIN 16  
= PIN 8  
DD  
SS  
D11 11  
*0 = Even Parity  
1 = Odd Parity  
NOTE:May redefine to suit application by manipulating W and/or other  
available D’s.  
ODD/EVEN W 10  
Q = D0  
D1  
D2  
D11  
W
REV 3  
1/94  
Motorola, Inc. 1995  
12345

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