MC14530

更新时间： 2024-11-28 22:58:11

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		栅
页数	文件大小	规格书
7页	220K
描述
Dual 5-Input Majority Logic Gate

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MC14530 数据手册

SEMICONDUCTOR TECHNICAL DATA

L SUFFIX

CERAMIC

CASE 620

The MC14530B dual five–input majority logic gate is constructed with

P–channel and N–channel enhancement mode devices in a single

monolithic structure. Combinational and sequential logic expressions are

easily implemented with the majority logic gate, often resulting in fewer

components than obtainable with the more basic gates. This device can also

provide numerous logic functions by using the W and some of the logic (A

thru E) inputs as control inputs.

P SUFFIX

PLASTIC

CASE 648

•

Diode Protection on All Inputs

Supply Voltage Range = 3.0 Vdc to 18 Vdc

Capable of Driving Two Low–power TTL Loads or One Low–power

Schottky TTL Load Over the Rated Temperature Range

D SUFFIX

SOIC

CASE 751B

ORDERING INFORMATION

MAXIMUM RATINGS* (Voltages Referenced to V

)

MC14XXXBCP

MC14XXXBCL

MC14XXXBD

Plastic

Ceramic

SOIC

Symbol

Parameter

DC Supply Voltage

Value

Unit

– 0.5 to + 18.0

= – 55° to 125°C for all packages.

V , V

Input or Output Voltage (DC or Transient)

– 0.5 to V

+ 0.5

in out

I , I

Input or Output Current (DC or Transient),

per Pin

± 10

in out

Power Dissipation, per Package†

Storage Temperature

500

BLOCK DIAGRAM

stg

– 65 to + 150

260

Lead Temperature (8–Second Soldering)

* Maximum Ratings are those values beyond which damage to the device may occur.

†Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C

Ceramic “L” Packages: – 12 mW/ C From 100 C To 125 C

LOGIC TABLE

* Z = M

Z = M

W = (ABC+ABD+ABE+ACD+

W = (ACE+ADE+BCD+BCE+

INPUTS A B C D E

W = (BDE+CDE)

For all combinations of inputs where three or

more inputs are logical “0”.

For all combinations of inputs where three or

more inputs are logical “1”.

* M is a logical “1” if any three or more

This device contains protection circuitry to guard against damage

due to high static voltages or electric fields. However, precautions must

be taken to avoid applications of any voltage higher than maximum rated

inputs are logical “1”.

Exclusive NOR Exclusive OR

TRUTH TABLE

voltages to this high-impedance circuit. For proper operation, V and

out

should be constrained to the range V

≤ (V or V ) ≤ V .

in out DD

Unused inputs must always be tied to an appropriate logic voltage

level (e.g., either V or V ). Unused outputs must be left open.

SS DD

= PIN 16

= PIN 8

REV 3

1/94

Motorola, Inc. 1995

MOTOROLA CMOS LOGIC DATA

MC14530B

12 3 4 5 6 7

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与MC14530相关器件

型号	品牌	获取价格	描述	数据表
MC14530B	MOTOROLA	获取价格	DUAL 5-INPUT MAJORITY LOGIC GATE
MC14530BAL	MOTOROLA	获取价格	4000/14000/40000 SERIES, DUAL 5-INPUT MAJORITY LOGIC GATE, CDIP16, 620-09
MC14530BALD	MOTOROLA	获取价格	4000/14000/40000 SERIES, DUAL 5-INPUT MAJORITY LOGIC GATE, CDIP16, 620-09
MC14530BALDS	MOTOROLA	获取价格	4000/14000/40000 SERIES, DUAL 5-INPUT MAJORITY LOGIC GATE, CDIP16, 620-09
MC14530BALS	MOTOROLA	获取价格	Majority Logic Gate, CMOS, CDIP16
MC14530BCL	MOTOROLA	获取价格	Dual 5-Input Majority Logic Gate
MC14530BCLD	MOTOROLA	获取价格	4000/14000/40000 SERIES, DUAL 5-INPUT MAJORITY LOGIC GATE, CDIP16, 620-09
MC14530BCLDS	MOTOROLA	获取价格	4000/14000/40000 SERIES, DUAL 5-INPUT MAJORITY LOGIC GATE, CDIP16, 620-09
MC14530BCLS	MOTOROLA	获取价格	Majority Logic Gate, CMOS, CDIP16
MC14530BCP	MOTOROLA	获取价格	Dual 5-Input Majority Logic Gate

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