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MC14530BCPDS

更新时间： 2024-11-04 13:11:15
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 栅
页数 文件大小 规格书
7页 220K
描述
4000/14000/40000 SERIES, DUAL 5-INPUT MAJORITY LOGIC GATE, PDIP16, 648-06

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MC14530BCPDS 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：DIP
包装说明：DIP, DIP16,.3针数：16
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.89系列：4000/14000/40000
JESD-30 代码：R-PDIP-T16JESD-609代码：e0
长度：20.07 mm负载电容（CL）：50 pF
逻辑集成电路类型：MAJORITY LOGIC GATE功能数量：2
输入次数：5端子数量：16
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：DIP
封装等效代码：DIP16,.3封装形状：RECTANGULAR
封装形式：IN-LINE峰值回流温度（摄氏度）：NOT SPECIFIED
电源：5/15 V传播延迟（tpd）：1200 ns
认证状态：Not Qualified施密特触发器：NO
座面最大高度：4.69 mm子类别：Gates
最大供电电压 (Vsup)：18 V最小供电电压 (Vsup)：3 V
标称供电电压 (Vsup)：5 V表面贴装：NO
技术：CMOS温度等级：INDUSTRIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：7.62 mm
Base Number Matches：1

MC14530BCPDS 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
L SUFFIX  
CERAMIC  
CASE 620  
The MC14530B dual five–input majority logic gate is constructed with  
P–channel and N–channel enhancement mode devices in a single  
monolithic structure. Combinational and sequential logic expressions are  
easily implemented with the majority logic gate, often resulting in fewer  
components than obtainable with the more basic gates. This device can also  
provide numerous logic functions by using the W and some of the logic (A  
thru E) inputs as control inputs.  
P SUFFIX  
PLASTIC  
CASE 648  
•
•
•
Diode Protection on All Inputs  
Supply Voltage Range = 3.0 Vdc to 18 Vdc  
Capable of Driving Two Low–power TTL Loads or One Low–power  
Schottky TTL Load Over the Rated Temperature Range  
D SUFFIX  
SOIC  
CASE 751B  
ORDERING INFORMATION  
MAXIMUM RATINGS* (Voltages Referenced to V  
)
SS  
MC14XXXBCP  
MC14XXXBCL  
MC14XXXBD  
Plastic  
Ceramic  
SOIC  
Symbol  
Parameter  
DC Supply Voltage  
Value  
Unit  
V
V
DD  
– 0.5 to + 18.0  
T
A
= – 55° to 125°C for all packages.  
V , V  
Input or Output Voltage (DC or Transient)  
– 0.5 to V  
DD  
+ 0.5  
V
in out  
I , I  
Input or Output Current (DC or Transient),  
per Pin  
± 10  
mA  
in out  
P
Power Dissipation, per Package†  
Storage Temperature  
500  
mW  
C
BLOCK DIAGRAM  
D
W
6
T
stg  
– 65 to + 150  
260  
T
Lead Temperature (8–Second Soldering)  
C
L
1
2
3
4
5
A
B
C
7
* Maximum Ratings are those values beyond which damage to the device may occur.  
†Temperature Derating:  
Z
M
5
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C  
Ceramic “L” Packages: – 12 mW/ C From 100 C To 125 C  
D
E
LOGIC TABLE  
* Z = M  
Z = M  
Z = M  
W = (ABC+ABD+ABE+ACD+  
W = (ACE+ADE+BCD+BCE+  
5
5
5
INPUTS A B C D E  
W
0
Z
1
0
0
1
W = (BDE+CDE)  
W
For all combinations of inputs where three or  
more inputs are logical “0”.  
A
B
9
10  
11  
12  
13  
1
For all combinations of inputs where three or  
more inputs are logical “1”.  
0
15  
Z
C
D
E
M
5
1
14  
W
* M is a logical “1” if any three or more  
5
This device contains protection circuitry to guard against damage  
due to high static voltages or electric fields. However, precautions must  
be taken to avoid applications of any voltage higher than maximum rated  
inputs are logical “1”.  
Exclusive NOR Exclusive OR  
TRUTH TABLE  
voltages to this high-impedance circuit. For proper operation, V and  
in  
V
out  
should be constrained to the range V  
SS  
≤ (V or V ) ≤ V .  
in out DD  
M
5
W
Z
Unused inputs must always be tied to an appropriate logic voltage  
level (e.g., either V or V ). Unused outputs must be left open.  
0
0
1
0
1
1
0
0
1
SS DD  
0
1
1
V
V
= PIN 16  
= PIN 8  
DD  
SS  
REV 3  
1/94  
Motorola, Inc. 1995  
1234567

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