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MC14040BDG PDF预览

MC14040BDG

更新时间: 2024-11-12 04:59:31
品牌 Logo 应用领域
安森美 - ONSEMI 计数器触发器逻辑集成电路光电二极管PC
页数 文件大小 规格书
8页 119K
描述
12−Bit Binary Counter

MC14040BDG 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Active零件包装代码:SOIC
包装说明:ROHS COMPLIANT. PLASTIC, SOIC-16针数:16
Reach Compliance Code:compliantHTS代码:8542.39.00.01
Factory Lead Time:1 week风险等级:0.49
Samacsys Confidence:3Samacsys Status:Released
Samacsys PartID:225144Samacsys Pin Count:16
Samacsys Part Category:Integrated CircuitSamacsys Package Category:Small Outline Packages
Samacsys Footprint Name:SOIC-16 CASE751B-05Samacsys Released Date:2015-08-07 09:46:40
Is Samacsys:N计数方向:UP
系列:4000/14000/40000JESD-30 代码:R-PDSO-G16
JESD-609代码:e3长度:9.9 mm
负载电容(CL):50 pF负载/预设输入:NO
逻辑集成电路类型:BINARY COUNTER最大频率@ Nom-Sup:1500000 Hz
工作模式:ASYNCHRONOUS湿度敏感等级:1
位数:12功能数量:1
端子数量:16最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP16,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:RAIL峰值回流温度(摄氏度):260
电源:5/15 V传播延迟(tpd):3250 ns
认证状态:Not Qualified座面最大高度:1.75 mm
子类别:Counters最大供电电压 (Vsup):18 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:Tin (Sn)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:40
触发器类型:NEGATIVE EDGE宽度:3.9 mm
最小 fmax:4.5 MHzBase Number Matches:1

MC14040BDG 数据手册

 浏览型号MC14040BDG的Datasheet PDF文件第2页浏览型号MC14040BDG的Datasheet PDF文件第3页浏览型号MC14040BDG的Datasheet PDF文件第4页浏览型号MC14040BDG的Datasheet PDF文件第5页浏览型号MC14040BDG的Datasheet PDF文件第6页浏览型号MC14040BDG的Datasheet PDF文件第7页 
MC14040B  
12−Bit Binary Counter  
The MC14040B 12−stage binary counter is constructed with MOS  
P−Channel and N−Channel enhancement mode devices in a single  
monolithic structure. This part is designed with an input wave shaping  
circuit and 12 stages of ripple−carry binary counter. The device  
advances the count on the negative−going edge of the clock pulse.  
Applications include time delay circuits, counter controls, and  
frequency−driving circuits.  
http://onsemi.com  
MARKING  
DIAGRAMS  
Features  
16  
1
Fully Static Operation  
Diode Protection on All Inputs  
Supply Voltage Range = 3.0 Vdc to 18 Vdc  
PDIP−16  
P SUFFIX  
CASE 648  
MC14040BCP  
AWLYYWWG  
Capable of Driving Two Low−power TTL Loads or One Low−power  
Schottky TTL Load Over the Rated Temperature Range  
Common Reset Line  
16  
SOIC−16  
D SUFFIX  
CASE 751B  
14040BG  
AWLYWW  
Pin−for−Pin Replacement for CD4040B  
Pb−Free Packages are Available*  
1
MAXIMUM RATINGS (Voltages Referenced to V  
)
SS  
16  
Symbol  
Parameter  
Value  
0.5 to +18.0  
Unit  
V
14  
040B  
ALYW  
TSSOP−16  
DT SUFFIX  
CASE 948F  
V
DC Supply Voltage Range  
DD  
V , V  
in out  
Input or Output Voltage Range  
(DC or Transient)  
0.5 to V + 0.5  
V
DD  
1
I , I  
Input or Output Current  
(DC or Transient) per Pin  
10  
mA  
in out  
16  
1
SOEIAJ−16  
F SUFFIX  
CASE 966  
P
T
Power Dissipation, per Package  
(Note 1)  
500  
mW  
MC14040B  
ALYWG  
D
Ambient Temperature Range  
Storage Temperature Range  
55 to +125  
65 to +150  
260  
°C  
°C  
°C  
A
T
stg  
A
WL, L  
YY, Y  
= Assembly Location  
= Wafer Lot  
T
Lead Temperature  
(8−Second Soldering)  
L
= Year  
WW, W = Work Week  
Maximum ratings are those values beyond which device damage can occur.  
Maximum ratings applied to the device are individual stress limit values (not  
normal operating conditions) and are not valid simultaneously. If these limits are  
exceeded, device functional operation is not implied, damage may occur and  
reliability may be affected.  
G
= Pb−Free Indicator  
1. Temperature Derating:  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 2 of this data sheet.  
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C  
This device contains protection circuitry to guard against damage due to high  
static voltages or electric fields. However, precautions must be taken to avoid  
applications of any voltage higher than maximum rated voltages to this  
high−impedance circuit. For proper operation, V and V should be constrained  
in  
out  
to the range V v (V or V ) v V  
.
DD  
SS  
in  
out  
Unused inputs must always be tied to an appropriate logic voltage level  
(e.g., either V or V ). Unused outputs must be left open.  
SS  
DD  
*For additional information on our Pb−Free strategy and soldering details, please  
download the ON Semiconductor Soldering and Mounting Techniques  
Reference Manual, SOLDERRM/D.  
©
Semiconductor Components Industries, LLC, 2005  
1
Publication Order Number:  
August, 2005 − Rev. 7  
MC14040B/D  
 

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