MC14001B Series
B-Suffix Series CMOS Gates
MC14001B, MC14011B, MC14023B,
MC14025B, MC14071B, MC14073B,
MC14081B, MC14082B
http://onsemi.com
The B Series logic gates are constructed with P and N channel
enhancement mode devices in a single monolithic structure
(Complementary MOS). Their primary use is where low power
dissipation and/or high noise immunity is desired.
MARKING
DIAGRAMS
14
PDIP–14
P SUFFIX
CASE 646
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• All Outputs Buffered
MC140xxBCP
AWLYYWW
• Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range.
• Double Diode Protection on All Inputs Except: Triple Diode
Protection on MC14011B and MC14081B
1
14
SOIC–14
D SUFFIX
CASE 751A
140xxB
AWLYWW
• Pin–for–Pin Replacements for Corresponding CD4000 Series B
Suffix Devices
1
14
TSSOP–14
DT SUFFIX
CASE 948G
14
0xxB
ALYW
MAXIMUM RATINGS (Voltages Referenced to V ) (Note 1.)
SS
Symbol
Parameter
Value
Unit
V
V
DD
DC Supply Voltage Range
–0.5 to +18.0
1
14
1
V , V
Input or Output Voltage Range
(DC or Transient)
–0.5 to V + 0.5
V
in out
DD
SOEIAJ–14
F SUFFIX
CASE 965
MC140xxB
ALYW
I , I
in out
Input or Output Current
(DC or Transient) per Pin
±10
mA
P
D
Power Dissipation,
500
mW
xx
A
WL, L
YY, Y
= Specific Device Code
= Assembly Location
= Wafer Lot
per Package (Note 2.)
T
A
Ambient Temperature Range
Storage Temperature Range
–55 to +125
–65 to +150
260
°C
°C
°C
= Year
T
stg
WW, W = Work Week
T
L
Lead Temperature
(8–Second Soldering)
DEVICE INFORMATION
1. Maximum Ratings are those values beyond which damage to the device
may occur.
Device
Description
2. Temperature Derating:
MC14001B
MC14011B
MC14023B
MC14025B
MC14071B
MC14073B
Quad 2–Input NOR Gate
Quad 2–Input NAND Gate
Triple 3–Input NAND Gate
Triple 3–Input NOR Gate
Quad 2–Input OR Gate
Triple 3–Input AND Gate
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high–impedance circuit. For proper operation, V and V should be constrained
in
out
to the range V v (V or V ) v V
.
SS
in
out
DD
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V or V ). Unused outputs must be left open.
SS
DD
MC14081B
MC14082B
Quad 2–Input AND Gate
Dual 4–Input AND Gate
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
Semiconductor Components Industries, LLC, 2000
1
Publication Order Number:
August, 2000 – Rev. 2
MC14001B/D