Datasheet > MC14001UB_06

MC14001UB_06

更新时间： 2024-11-04 04:59:35

品牌	Logo	应用领域
安森美 - ONSEMI		栅
页数	文件大小	规格书
7页	147K
描述
UB−Suffix Series CMOS Gates

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中文翻译

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数据手册

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MC14001UB_06 数据手册

MC14001UB, MC14011UB

UB−Suffix Series

CMOS Gates

The UB Series logic gates are constructed with P and N channel

enhancement mode devices in a single monolithic structure

(Complementary MOS). Their primary use is where low power

dissipation and/or high noise immunity is desired. The UB set of

CMOS gates are inverting non−buffered functions.

http://onsemi.com

MARKING

Features

DIAGRAMS

• Supply Voltage Range = 3.0 Vdc to 18 Vdc

• Linear and Oscillator Applications

• Capable of Driving Two Low−Power TTL Loads or One

Low−Power Schottky TTL Load Over the Rated Temperature Range

• Double Diode Protection on All Inputs

PDIP−14

P SUFFIX

CASE 646

MC140xxUBCP

AWLYYWWG

• Pin−for−Pin Replacements for Corresponding CD4000 Series UB

Suffix Devices

• Pb−Free Packages are Available

SOIC−14

D SUFFIX

CASE 751A

140xxUG

AWLYWW

MAXIMUM RATINGS (Voltages Referenced to V

)

Symbol

Parameter

Value

Unit

DC Supply Voltage Range

−0.5 to +18.0

V , V

Input or Output Voltage Range

(DC or Transient)

−0.5 to V + 0.5

WL, L

YY, Y

= Specific Device Code

= Assembly Location

= Wafer Lot

in out

I , I

in out

Input or Output Current

(DC or Transient) per Pin

±10

= Year

WW, W = Work Week

= Pb−Free Package

Power Dissipation, per Package

(Note 1)

500

Ambient Temperature Range

Storage Temperature Range

−55 to +125

−65 to +150

260

°C

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 4 of this data sheet.

stg

Lead Temperature

(8−Second Soldering)

Stresses exceeding Maximum Ratings may damage the device. Maximum

Ratings are stress ratings only. Functional operation above the Recommended

Operating Conditions is not implied. Extended exposure to stresses above the

Recommended Operating Conditions may affect device reliability.

1. Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C

This device contains protection circuitry to guard against damage due to high

static voltages or electric fields. However, precautions must be taken to avoid

applications of any voltage higher than maximum rated voltages to this

high−impedance circuit. For proper operation, V and V should be constrained

out

to the range V v (V or V ) v V

out

Unused inputs must always be tied to an appropriate logic voltage level

(e.g., either V or V ). Unused outputs must be left open.

Semiconductor Components Industries, LLC, 2006

Publication Order Number:

October, 2006 − Rev. 6

MC14001UB/D

12 3 4 5 6 7

中文翻译

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与MC14001UB_06相关器件

型号	品牌	获取价格	描述	数据表
MC14001UB_09	ONSEMI	获取价格	UB-Suffix Series CMOS Gates
MC14001UBAL	MOTOROLA	获取价格	暂无描述
MC14001UBAL	ONSEMI	获取价格	NOR GATE
MC14001UBALD	MOTOROLA	获取价格	4000/14000/40000 SERIES, QUAD 2-INPUT NOR GATE, CDIP14, 632-08
MC14001UBALDS	MOTOROLA	获取价格	NOR Gate, 4000/14000/40000 Series, 4-Func, 2-Input, CMOS, CDIP14, 632-08
MC14001UBALS	MOTOROLA	获取价格	NOR Gate, CMOS, CDIP14
MC14001UBCL	MOTOROLA	获取价格	UB-Suffix Series COMS Gates
MC14001UBCLD	MOTOROLA	获取价格	NOR Gate, 4000/14000/40000 Series, 4-Func, 2-Input, CMOS, CDIP14, 632-08
MC14001UBCLDS	MOTOROLA	获取价格	NOR Gate, 4000/14000/40000 Series, 4-Func, 2-Input, CMOS, CDIP14, 632-08
MC14001UBCLS	MOTOROLA	获取价格	NOR Gate, CMOS, CDIP14

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