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MC10H642FNG

更新时间： 2024-11-19 04:59:39
品牌 Logo 应用领域
安森美 - ONSEMI 时钟驱动器逻辑集成电路
页数 文件大小 规格书
10页 173K
描述
68030/040 PECL to TTL Clock Driver

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中文翻译

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MC10H642FNG 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：QLCC包装说明：LEAD FREE, PLASTIC, LCC-28
针数：28Reach Compliance Code：unknown
HTS代码：8542.39.00.01风险等级：8.07
Is Samacsys：N系列：10H
输入调节：DIFFERENTIAL MUXJESD-30 代码：S-PQCC-J28
JESD-609代码：e3长度：11.505 mm
逻辑集成电路类型：LOW SKEW CLOCK DRIVER最大I（ol）：0.024 A
功能数量：1反相输出次数：
端子数量：28实输出次数：8
最高工作温度：85 °C最低工作温度：
封装主体材料：PLASTIC/EPOXY封装代码：QCCJ
封装等效代码：LDCC28,.5SQ封装形状：SQUARE
封装形式：CHIP CARRIER峰值回流温度（摄氏度）：260
电源：5 VProp。Delay @ Nom-Sup：6.5 ns
传播延迟（tpd）：5.75 ns认证状态：Not Qualified
Same Edge Skew-Max（tskwd）：0.5 ns座面最大高度：4.57 mm
子类别：Clock Drivers最大供电电压 (Vsup)：5.25 V
最小供电电压 (Vsup)：4.75 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：ECL
温度等级：OTHER端子面层：Tin (Sn)
端子形式：J BEND端子节距：1.27 mm
端子位置：QUAD处于峰值回流温度下的最长时间：40
宽度：11.505 mm最小 fmax：100 MHz
Base Number Matches：1

MC10H642FNG 数据手册

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MC10H642, MC100H642  
68030/040 PECL to TTL  
Clock Driver  
Description  
The MC10H/100H642 generates the necessary clocks for the  
68030, 68040 and similar microprocessors. It is guaranteed to meet the  
clock specifications required by the 68030 and 68040 in terms of  
part−to−partskew, within−part skew and also duty cycle skew.  
The user has a choice of using either TTL or PECL (ECL referenced  
to +5.0 V) for the input clock. TTL clocks are typically used in present  
MPU systems. However, as clock speeds increase to 50 MHz and  
beyond, the inherent superiority of ECL (particularly differential  
ECL) as a means of clock signal distribution becomes increasingly  
evident. The H642 also uses differential PECL internally to achieve its  
superior skew characteristic.  
The H642 includes divide−by−two and divide−by−four stages, both  
to achieve the necessary duty cycle skew and to generate MPU clocks  
as required. A typical 50 MHz processor application would use an  
input clock running at 100 MHz, thus obtaining output clocks at  
50 MHz and 25 MHz (see Logic Diagram).  
http://onsemi.com  
PLCC−28  
FN SUFFIX  
CASE 776  
MARKING DIAGRAM*  
The 10H version is compatible with MECL 10H™ ECL logic levels,  
while the 100H version is compatible with 100K levels (referenced to  
+5.0 V).  
1
MCxxxH642G  
AWLYYWW  
Features  
• Generates Clocks for 68030/040  
• Meets 030/040 Skew Requirements  
• TTL or PECL Input Clock  
• Extra TTL and PECL Power/Ground Pins  
• Asynchronous Reset  
xxx  
A
WL  
YY  
WW  
G
= 10 or 100  
= Assembly Location  
= Wafer Lot  
= Year  
= Work Week  
= Pb−Free Package  
• Single +5.0 V Supply  
• Pb−Free Packages are Available*  
Function  
Reset(R): LOW on RESET forces all Q outputs LOW.  
Select(SEL): LOW selects the ECL input source (DE/DE). HIGH  
selects the TTL input source (DT).  
*For additional marking information, refer to  
Application Note AND8002/D.  
The H642 also contains circuitry to force a stable input state of the  
ECL differential input pair, should both sides be left open. In this Case,  
the DE side of the input is pulled LOW, and DE goes HIGH.  
Power Up: The device is designed to have positive edges of the ÷2  
and ÷4 outputs synchronized at Power Up.  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 8 of this data sheet.  
*For additional information on our Pb−Free strategy and soldering details, please  
download the ON Semiconductor Soldering and Mounting Techniques  
Reference Manual, SOLDERRM/D.  
©
Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
November, 2006 − Rev. 8  
MC10H642/D  
1234567...10

中文翻译

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MC10H642FNG 替代型号

型号 品牌 替代类型 描述 数据表
MC10H642FNR2G ONSEMI

完全替代

 68030/040 PECL to TTL Clock Driver
MC10H642FNR2 ONSEMI

完全替代

 68030/040 PECL to TTL Clock Driver
MC10H642FN ONSEMI

完全替代

 68030/040 PECL to TTL Clock Driver

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