MC10H642

更新时间： 2024-11-18 22:58:11

品牌	Logo	应用领域
安森美 - ONSEMI		时钟驱动器
页数	文件大小	规格书
9页	243K
描述
68030/040 PECL-TTL CLOCK DRIVER

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

MC10H642 数据手册

SEMICONDUCTOR TECHNICAL DATA

The MC10H/100H642 generates the necessary clocks for the 68030,

68040 and similar microprocessors. It is guaranteed to meet the clock

specifications required by the 68030 and 68040 in terms of part–to–part

skew, within–part skew and also duty cycle skew.

The user has a choice of using either TTL or PECL (ECL referenced to

+5.0V) for the input clock. TTL clocks are typically used in present MPU

systems. However, as clock speeds increase to 50MHz and beyond, the

inherent superiority of ECL (particularly differential ECL) as a means of

clock signal distribution becomes increasingly evident. The H642 also

uses differential PECL internally to achieve its superior skew

characteristic.

68030/040

PECL–TTL CLOCK

DRIVER

The H642 includes divide–by–two and divide–by–four stages, both to

achieve the necessary duty cycle skew and to generate MPU clocks as

required. A typical 50MHz processor application would use an input clock

running at 100MHz, thus obtaining output clocks at 50MHz and 25MHz

(see Logic Diagram).

The 10H version is compatible with MECL 10H ECL logic levels,

while the 100H version is compatible with 100K levels (referenced to

+5.0V).

• Generates Clocks for 68030/040

• Meets 030/040 Skew Requirements

• TTL or PECL Input Clock

FN SUFFIX

PLASTIC PACKAGE

CASE 776–02

• Extra TTL and PECL Power/Ground Pins

• Asynchronous Reset

• Single +5.0V Supply

Function

Reset(R):

LOW on RESET forces all Q outputs LOW.

Select(SEL): LOW selects the ECL input source (DE/DE).

HIGH selects the TTL input source (DT).

The H642 also contains circuitry to force a stable input state of the ECL differential input pair, should both sides be left open. In

this Case, the DE side of the input is pulled LOW, and DE goes HIGH.

Power Up:

The device is designed to have positive edges of the ÷2 and ÷4 outputs synchronized at Power Up.

VT VT Q1

GT GT Q0

22 21 20

Q2 26

GT 27

GT 28

Pinout: 28–Lead PLCC

(Top View)

GT GT

Q6 Q7

VT SEL

9/96

Motorola, Inc. 1996

REV 4

2–1

12 3 4 5 6 7...9

中文翻译

下载PDF

与MC10H642相关器件

型号	品牌	获取价格	描述	数据表
MC10H642_06	ONSEMI	获取价格	68030/040 PECL to TTL Clock Driver
MC10H642FN	ONSEMI	获取价格	68030/040 PECL to TTL Clock Driver
MC10H642FN	MOTOROLA	获取价格	68030/040 PECL-TTL CLOCK DRIVER
MC10H642FNG	ONSEMI	获取价格	68030/040 PECL to TTL Clock Driver
MC10H642FNR2	ONSEMI	获取价格	68030/040 PECL to TTL Clock Driver
MC10H642FNR2G	ONSEMI	获取价格	68030/040 PECL to TTL Clock Driver
MC10H643	ONSEMI	获取价格	DUAL SUPPLY ECL-TTL 1:8 CLOCK DRIVER
MC10H643_06	ONSEMI	获取价格	Dual Supply ECL to TTL 1:8 Clock Driver
MC10H643FN	ONSEMI	获取价格	Dual Supply ECL to TTL 1:8 Clock Driver
MC10H643FN	MOTOROLA	获取价格	DUAL SUPPLY ECL-TTL 1:8 CLOCK DRIVER