Datasheet > MC10H640

MC10H640

更新时间： 2024-11-18 22:33:11

品牌	Logo	应用领域
安森美 - ONSEMI		时钟驱动器
页数	文件大小	规格书
8页	137K
描述
PECL-TTL CLOCK DRIVER

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数据手册

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MC10H640 数据手册

SEMICONDUCTOR TECHNICAL DATA

The MC10H/100H640 generates the necessary clocks for the 68030,

68040 and similar microprocessors. It is guaranteed to meet the clock

specifications required by the 68030 and 68040 in terms of part–to–part

skew, within–part skew and also duty cycle skew.

The user has a choice of using either TTL or PECL (ECL referenced to

+5.0V) for the input clock. TTL clocks are typically used in present MPU

systems. However, as clock speeds increase to 50MHz and beyond, the

inherent superiority of ECL (particularly differential ECL) as a means of

clock signal distribution becomes increasingly evident. The H640 also

uses differential PECL internally to achieve its superior skew

characteristic.

68030/040

PECL–TTL CLOCK

DRIVER

The H640 includes divide–by–two and divide–by–four stages, both to

achieve the necessary duty cycle skew and to generate MPU clocks as

required. A typical 50MHz processor application would use an input clock

running at 100MHz, thus obtaining output clocks at 50MHz and 25MHz

(see Logic Symbol).

The 10H version is compatible with MECL 10H ECL logic levels,

while the 100H version is compatible with 100K levels (referenced

to +5.0V).

FN SUFFIX

PLASTIC PACKAGE

CASE 776–02

• Generates Clocks for 68030/040

• Meets 030/040 Skew Requirements

• TTL or PECL Input Clock

• Extra TTL and PECL Power/Ground Pins

• Asynchronous Reset

• Single +5.0V Supply

Function

Reset (R): LOW on RESET forces all Q outputs LOW and all Q outputs HIGH.

Power–Up: The device is designed to have the POS edges of the ÷2 and ÷4 outputs synchronized at power up.

Select (SEL): LOW selects the ECL input source (DE/DE). HIGH selects the TTL input source (DT).

The H640 also contains circuitry to force a stable state of the ECL input differential pair, should both sides be left open. In this

case, the DE side of the input is pulled LOW, and DE goes HIGH.

VT VT Q1

GT GT Q0

22 21 20

Q2 26

GT 27

GT 28

Pinout: 28–Lead PLCC

(Top View)

GT GT

Q4 Q5

VT SEL

11/93

Motorola, Inc. 1996

REV 3

2–1

12 3 4 5 6 7 8

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与MC10H640相关器件

型号	品牌	获取价格	描述	数据表
MC10H640_06	ONSEMI	获取价格	68030/040 PECL to TTL Clock Driver
MC10H640FN	MOTOROLA	获取价格	68030/040 PECL-TTL CLOCK DRIVER
MC10H640FN	ONSEMI	获取价格	68030/040 PECL to TTL Clock Driver
MC10H640FNG	ONSEMI	获取价格	68030/040 PECL to TTL Clock Driver
MC10H640FNR2	ONSEMI	获取价格	68030/040 PECL to TTL Clock Driver
MC10H640FNR2G	ONSEMI	获取价格	68030/040 PECL to TTL Clock Driver
MC10H641	ONSEMI	获取价格	SINGLE SUPPLY PECL-TTL 1:9 CLOCK DISTRIBUTION CHIP
MC10H641_06	ONSEMI	获取价格	Single Supply PECL to TTL 1:9 Clock Distribution Chip
MC10H641FN	MOTOROLA	获取价格	SINGLE SUPPLY PECL-TTL 1:9 CLOCK DISTRIBUTION CHIP
MC10H641FN	ROCHESTER	获取价格	10H SERIES, LOW SKEW CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC28, PLASTIC