Datasheet > MC10H640_06

MC10H640_06

更新时间： 2024-11-19 04:59:39

品牌	Logo	应用领域
安森美 - ONSEMI		时钟驱动器
页数	文件大小	规格书
9页	140K
描述
68030/040 PECL to TTL Clock Driver

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数据手册

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MC10H640_06 数据手册

MC10H640, MC100H640

68030/040 PECL to TTL

Clock Driver

Description

The MC10H/100H640 generates the necessary clocks for the

68030, 68040 and similar microprocessors. It is guaranteed to meet the

clock specifications required by the 68030 and 68040 in terms of

part−to−partskew, within−part skew and also duty cycle skew.

The user has a choice of using either TTL or PECL (ECL referenced

to +5.0 V) for the input clock. TTL clocks are typically used in present

MPU systems. However, as clock speeds increase to 50 MHz and

beyond, the inherent superiority of ECL (particularly differential

ECL) as a means of clock signal distribution becomes increasingly

evident. The H640 also uses differential PECL internally to achieve its

superior skew characteristic.

The H640 includes divide−by−two and divide−by−four stages, both

to achieve the necessary duty cycle skew and to generate MPU clocks

as required. A typical 50 MHz processor application would use an

input clock running at 100 MHz, thus obtaining output clocks at

50 MHz and 25 MHz (see Logic Diagram).

http://onsemi.com

PLCC−28

FN SUFFIX

CASE 776

MARKING DIAGRAM*

Features

• Generates Clocks for 68030/040

• Meets 030/040 Skew Requirements

• TTL or PECL Input Clock

• Extra TTL and PECL Power/Ground Pins

• Asynchronous Reset

MCxxxH640G

AWLYYWW

• Single +5.0 V Supply

• Pb−Free Packages are Available*

xxx

= 10 or 100

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb−Free Package

Function

Reset (R): LOW on RESET forces all Q outputs LOW and all Q

outputs HIGH.

Power−Up:The device is designed to have the POS edges of the ÷ 2

and ÷ 4 outputs synchronized at power up.

Select (SEL): LOW selects the ECL input source (DE/DE). HIGH

selects the TTL input source (DT).

*For additional marking information, refer to

Application Note AND8002/D.

The H640 also contains circuitry to force a stable state of the ECL

input differential pair, should both sides be left open. In this case, the

DE side of the input is pulled LOW, and DE goes HIGH.

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 7 of this data sheet.

*For additional information on our Pb−Free strategy and soldering details, please

download the ON Semiconductor Soldering and Mounting Techniques

Reference Manual, SOLDERRM/D.

Semiconductor Components Industries, LLC, 2006

Publication Order Number:

November, 2006 − Rev. 8

MC10H640/D

12 3 4 5 6 7...9

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与MC10H640_06相关器件

型号	品牌	获取价格	描述	数据表
MC10H640FN	MOTOROLA	获取价格	68030/040 PECL-TTL CLOCK DRIVER
MC10H640FN	ONSEMI	获取价格	68030/040 PECL to TTL Clock Driver
MC10H640FNG	ONSEMI	获取价格	68030/040 PECL to TTL Clock Driver
MC10H640FNR2	ONSEMI	获取价格	68030/040 PECL to TTL Clock Driver
MC10H640FNR2G	ONSEMI	获取价格	68030/040 PECL to TTL Clock Driver
MC10H641	ONSEMI	获取价格	SINGLE SUPPLY PECL-TTL 1:9 CLOCK DISTRIBUTION CHIP
MC10H641_06	ONSEMI	获取价格	Single Supply PECL to TTL 1:9 Clock Distribution Chip
MC10H641FN	MOTOROLA	获取价格	SINGLE SUPPLY PECL-TTL 1:9 CLOCK DISTRIBUTION CHIP
MC10H641FN	ROCHESTER	获取价格	10H SERIES, LOW SKEW CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC28, PLASTIC
MC10H641FN	ONSEMI	获取价格	Single Supply PECL to TTL 1:9 Clock Distribution Chip

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