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MC10H640FNR2G PDF预览

MC10H640FNR2G

更新时间: 2024-11-19 04:59:39
品牌 Logo 应用领域
安森美 - ONSEMI 时钟驱动器逻辑集成电路
页数 文件大小 规格书
9页 140K
描述
68030/040 PECL to TTL Clock Driver

MC10H640FNR2G 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:QLCC
包装说明:QCCJ, LDCC28,.5SQ针数:28
Reach Compliance Code:compliantHTS代码:8542.39.00.01
Factory Lead Time:1 week风险等级:5.36
系列:10H输入调节:DIFFERENTIAL MUX
JESD-30 代码:S-PQCC-J28JESD-609代码:e3
长度:11.505 mm逻辑集成电路类型:LOW SKEW CLOCK DRIVER
最大I(ol):0.024 A功能数量:1
反相输出次数:端子数量:28
实输出次数:6最高工作温度:85 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装等效代码:LDCC28,.5SQ
封装形状:SQUARE封装形式:CHIP CARRIER
峰值回流温度(摄氏度):260电源:5 V
Prop。Delay @ Nom-Sup:7 ns传播延迟(tpd):6 ns
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.5 ns
座面最大高度:4.57 mm子类别:Clock Drivers
最大供电电压 (Vsup):5.25 V最小供电电压 (Vsup):4.75 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:ECL温度等级:OTHER
端子面层:Tin (Sn)端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
处于峰值回流温度下的最长时间:40宽度:11.505 mm
最小 fmax:135 MHzBase Number Matches:1

MC10H640FNR2G 数据手册

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MC10H640, MC100H640  
68030/040 PECL to TTL  
Clock Driver  
Description  
The MC10H/100H640 generates the necessary clocks for the  
68030, 68040 and similar microprocessors. It is guaranteed to meet the  
clock specifications required by the 68030 and 68040 in terms of  
parttopartskew, withinpart skew and also duty cycle skew.  
The user has a choice of using either TTL or PECL (ECL referenced  
to +5.0 V) for the input clock. TTL clocks are typically used in present  
MPU systems. However, as clock speeds increase to 50 MHz and  
beyond, the inherent superiority of ECL (particularly differential  
ECL) as a means of clock signal distribution becomes increasingly  
evident. The H640 also uses differential PECL internally to achieve its  
superior skew characteristic.  
The H640 includes dividebytwo and dividebyfour stages, both  
to achieve the necessary duty cycle skew and to generate MPU clocks  
as required. A typical 50 MHz processor application would use an  
input clock running at 100 MHz, thus obtaining output clocks at  
50 MHz and 25 MHz (see Logic Diagram).  
http://onsemi.com  
PLCC28  
FN SUFFIX  
CASE 776  
MARKING DIAGRAM*  
Features  
1
Generates Clocks for 68030/040  
Meets 030/040 Skew Requirements  
TTL or PECL Input Clock  
Extra TTL and PECL Power/Ground Pins  
Asynchronous Reset  
MCxxxH640G  
AWLYYWW  
Single +5.0 V Supply  
PbFree Packages are Available*  
xxx  
A
WL  
YY  
WW  
G
= 10 or 100  
= Assembly Location  
= Wafer Lot  
= Year  
= Work Week  
= PbFree Package  
Function  
Reset (R): LOW on RESET forces all Q outputs LOW and all Q  
outputs HIGH.  
PowerUp:The device is designed to have the POS edges of the ÷ 2  
and ÷ 4 outputs synchronized at power up.  
Select (SEL): LOW selects the ECL input source (DE/DE). HIGH  
selects the TTL input source (DT).  
*For additional marking information, refer to  
Application Note AND8002/D.  
The H640 also contains circuitry to force a stable state of the ECL  
input differential pair, should both sides be left open. In this case, the  
DE side of the input is pulled LOW, and DE goes HIGH.  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 7 of this data sheet.  
*For additional information on our PbFree strategy and soldering details, please  
download the ON Semiconductor Soldering and Mounting Techniques  
Reference Manual, SOLDERRM/D.  
©
Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
November, 2006 Rev. 8  
MC10H640/D  

MC10H640FNR2G 替代型号

型号 品牌 替代类型 描述 数据表
MC10H640FNR2 ONSEMI

完全替代

68030/040 PECL to TTL Clock Driver

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