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MC10H176 PDF预览

MC10H176

更新时间: 2024-11-03 22:58:11
品牌 Logo 应用领域
安森美 - ONSEMI 触发器
页数 文件大小 规格书
4页 101K
描述
Hex D Master-Slave Flip-Flop

MC10H176 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
The MC10H176 contains six master slave type D flip–flops with a common  
clock. This MECL 10H part is a functional/pinout duplication of the standard  
MECL 10K family part, with 100% improvement in clock frequency and  
propagation delay and no increase in power–supply current.  
Propagation Delay, 1.7 ns Typical  
Power Dissipation, 460 mW Typical  
Improved Noise Margin 150 mV (Over Operating Voltage and  
Temperature Range)  
Voltage Compensated  
MECL 10K–Compatible  
L SUFFIX  
CERAMIC PACKAGE  
CASE 620–10  
P SUFFIX  
PLASTIC PACKAGE  
CASE 648–08  
MAXIMUM RATINGS  
FN SUFFIX  
PLCC  
CASE 775–02  
Characteristic  
Symbol  
Rating  
Unit  
Vdc  
Vdc  
mA  
Power Supply (V  
= 0)  
V
EE  
–8.0 to 0  
CC  
Input Voltage (V  
= 0)  
V
I
0 to V  
CC  
EE  
Output CurrentContinuous  
— Surge  
I
out  
50  
100  
CLOCKED TRUTH TABLE  
Operating Temperature Range  
T
A
0 to +75  
°C  
Storage Temperature RangePlastic  
— Ceramic  
T
–55 to +150  
–55 to +165  
°C  
°C  
C
Q
X
L
Q
n+1  
Q
n
stg  
L
ELECTRICAL CHARACTERISTICS (V  
0°  
= –5.2 V ±5%) (See Note)  
H *  
H *  
L
EE  
H
H
25°  
75°  
Characteristic  
Symbol Min  
Max  
Min  
Max  
Min  
Max  
Unit  
* A clock H is a clock transition from  
a low to a high state.  
Power Supply Current  
I
E
123  
112  
123  
mA  
Input Current High  
Pins 5,6,7,10,11,12  
Pin 9  
I
µA  
inH  
425  
670  
265  
420  
265  
420  
Input Current Low  
High Output Voltage  
Low Output Voltage  
High Input Voltage  
Low Input Voltage  
I
0.5  
0.5  
0.3  
µA  
inL  
DIP  
V
–1.02 –0.84 –0.98 –0.81 –0.92 –0.735 Vdc  
–1.95 –1.63 –1.95 –1.63 –1.95 –1.60 Vdc  
–1.17 –0.84 –1.13 –0.81 –1.07 –0.735 Vdc  
PIN ASSIGNMENT  
OH  
V
OL  
V
V
V
CC2  
IH  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
CC1  
V
–1.95 –1.48 –1.95 –1.48 –1.95 –1.45  
Vdc  
IL  
Q5  
Q0  
AC PARAMETERS  
Propagation Delay  
Set–up Time  
Hold Time  
Q1  
Q2  
D0  
D1  
D2  
Q4  
t
0.9  
1.5  
0.9  
0.5  
0.5  
250  
2.1  
0.9  
1.5  
0.9  
0.5  
0.5  
250  
2.2  
1.0  
1.5  
1.0  
0.5  
0.5  
250  
2.4  
ns  
ns  
pd  
Q3  
t
set  
t
ns  
D5  
hold  
Rise Time  
t
r
1.8  
1.8  
1.9  
1.9  
2.0  
2.0  
ns  
D4  
Fall Time  
t
f
ns  
D3  
Toggle Frequency  
NOTE:  
f
MHz  
tog  
V
CLOCK  
EE  
Each MECL 10H series circuit has been designed to meet the dc specifications shown in the test  
table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a  
printed circuit board and transverse air flow greater than 500 linear fpm is maintained. Outputs are  
terminated through a 50–ohm resistor to –2.0 volts.  
Pin assignment is for Dual–in–Line Package.  
For PLCC pin assignment, see the Pin Conversion  
Tables on page 6–11 of the Motorola MECL Data  
Book (DL122/D).  
3/93  
Motorola, Inc. 1996  
REV 5  

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