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MC10H130L PDF预览

MC10H130L

更新时间: 2024-11-12 05:10:23
品牌 Logo 应用领域
安森美 - ONSEMI 触发器锁存器逻辑集成电路
页数 文件大小 规格书
5页 141K
描述
Dual Latch

MC10H130L 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:DIP包装说明:CERAMIC, DIP-16
针数:16Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.4
Is Samacsys:N系列:10H
JESD-30 代码:R-GDIP-T16JESD-609代码:e0
长度:19.49 mm逻辑集成电路类型:D LATCH
位数:2功能数量:1
端子数量:16最高工作温度:75 °C
最低工作温度:输出特性:OPEN-EMITTER
输出极性:COMPLEMENTARY封装主体材料:CERAMIC, GLASS-SEALED
封装代码:DIP封装等效代码:DIP16,.3
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):235Prop。Delay @ Nom-Sup:1.9 ns
传播延迟(tpd):1.7 ns认证状态:Not Qualified
座面最大高度:5.08 mm子类别:FF/Latches
表面贴装:NO技术:ECL
温度等级:COMMERCIAL EXTENDED端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:LOW LEVEL宽度:7.62 mm
Base Number Matches:1

MC10H130L 数据手册

 浏览型号MC10H130L的Datasheet PDF文件第2页浏览型号MC10H130L的Datasheet PDF文件第3页浏览型号MC10H130L的Datasheet PDF文件第4页浏览型号MC10H130L的Datasheet PDF文件第5页 
MC10H130  
Dual Latch  
Description  
The MC10H130 is a MECL 10Hpart which is a functional/pinout  
duplication of the standard MECL 10Kfamily part, with 100%  
improvement in clock speed and propagation delay and no increase in  
power supply current.  
http://onsemi.com  
MARKING DIAGRAMS*  
Features  
Propagation Delay, 1.0 ns Typical  
Power Dissipation, 155 mW Typical  
16  
Improved Noise Margin 150 mV (Over Operating Voltage and  
MC10H130L  
AWLYYWW  
Temperature Range)  
Voltage Compensated  
1
MECL 10K Compatible  
CDIP16  
L SUFFIX  
CASE 620A  
PbFree Packages are Available*  
S1  
5
Table 1. TRUTH TABLE  
2
3
Q1  
Q1  
D1  
CE1  
7
6
D
C
CE  
Q
n+1  
L
H
X
X
X
L
L
L
L
L
16  
1
H
L
H
L
Q
n
n
n
MC10H130P  
AWLYYWWG  
16  
V
= PIN 1  
= PIN 16  
H
H
Q
R1  
C
4
9
CC1  
CC2  
H
Q
V
V
1
R2 13  
= PIN 8  
EE  
PDIP16  
P SUFFIX  
CASE 648  
14  
Q2  
CE2 11  
D2 10  
15  
Q2  
S2 12  
1 20  
Figure 1. Logic Diagram  
10H130G  
AWLYYWW  
20  
1
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
V
V
CC2  
CC1  
PLLC20  
FN SUFFIX  
CASE 775  
Q1  
Q2  
Q2  
R2  
S2  
Q1  
R1  
S1  
A
= Assembly Location  
= Wafer Lot  
= Year  
= Work Week  
= PbFree Package  
C
C
E2  
E1  
WL  
YY  
WW  
G
D1  
D2  
C
V
EE  
Pin assignment is for DualinLine Package.  
Figure 2. Pin Assignment  
*For additional marking information, refer to  
Application Note AND8002/D.  
*For additional information on our PbFree strategy and soldering details, please  
download the ON Semiconductor Soldering and Mounting Techniques  
Reference Manual, SOLDERRM/D.  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 3 of this data sheet.  
©
Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
February, 2006 Rev. 8  
MC10H130/D  

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