MC10EL33, MC100EL33
5VꢀECL ÷4 Divider
Description
The MC10EL/100EL33 is an integrated ÷4 divider. The differential
clock inputs and the V allow a differential, single-ended or AC coupled
BB
interface to the device. The V pin, an internally generated voltage
BB
supply, is available to this device only. For single-ended input conditions,
the unused differential input is connected to V as a switching reference
BB
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MARKING
voltage. V may also rebias AC coupled inputs. When used, decouple
BB
V
BB
and V via a 0.01 mF capacitor and limit current sourcing or sinking
CC
to 0.5 mA. When not used, V should be left open.
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DIAGRAMS*
The reset pin is asynchronous and is asserted on the rising edge. Upon
power-up, the internal flip-flops will attain a random state; the reset allows
for the synchronization of multiple EL33’s in a system.
The 100 Series contains temperature compensation.
Features
8
8
1
8
1
HEL33
KEL33
ALYW
G
ALYW
G
SOIC−8
D SUFFIX
CASE 751
• 650 ps Propagation Delay
• 4.0 GHz Toggle Frequency
1
• ESD Protection: Human Body Model; > 1 kV,
8
1
8
8
Machine Model; > 100 V
1
HL33
ALYWG
G
KL33
ALYWG
G
• PECL Mode Operating Range: V = 4.2 V to 5.7 V with V = 0 V
CC
EE
• NECL Mode Operating Range: V = 0 V with V = −4.2 V to −5.7 V
CC
EE
TSSOP−8
DT SUFFIX
CASE 948R
• Internal Input Pulldown Resistors on CLK(s) and R.
1
• Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
• Moisture Sensitivity Level 1
For Additional Information, see Application Note AND8003/D
• Flammability Rating: UL 94 V−0 @ 0.125 in,
Oxygen Index: 28 to 34
• Transistor Count = 95 devices
• Pb−Free Packages are Available
1
4
1
4
DFN8
MN SUFFIX
CASE 506AA
Reset
CLK
1
2
8
7
V
H = MC10
L
Y
= Wafer Lot
= Year
CC
K
= MC100
4V = MC10
2K = MC100
W = Work Week
M = Date Code
G
R
Q
Q
A
= Assembly Location
= Pb−Free Package
÷4
(Note: Microdot may be in either location)
CLK
3
4
6
5
*For additional marking information, refer to
Application Note AND8002/D.
V
BB
V
EE
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
Figure 1. Logic Diagram and Pinout Assignment
© Semiconductor Components Industries, LLC, 2008
1
Publication Order Number:
August, 2008 − Rev. 10
MC10EL33/D