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MC10176PD PDF预览

MC10176PD

更新时间: 2024-11-04 12:58:51
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 触发器逻辑集成电路
页数 文件大小 规格书
5页 110K
描述
D Flip-Flop, 6-Func, Master-slave Triggered, ECL10K, PDIP16

MC10176PD 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
Reach Compliance Code:unknown风险等级:5.87
JESD-30 代码:R-PDIP-T16JESD-609代码:e0
逻辑集成电路类型:D FLIP-FLOP功能数量:6
端子数量:16最高工作温度:85 °C
最低工作温度:-30 °C封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP16,.3
封装形状:RECTANGULAR封装形式:IN-LINE
电源:-5.2 V子类别:FF/Latches
表面贴装:NO技术:ECL10K
温度等级:OTHER端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL触发器类型:MASTER-SLAVE
Base Number Matches:1

MC10176PD 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
The MC10176 contains six high-speed, master slave type “D” flip-flops.  
Clocking is common to all six flip-flops. Data is entered into the master when the  
clock is low. Master to slave data transfer takes place on the positive-going  
Clock transition. Thus, outputs may change only on a positive-going Clock  
transition. A change in the information present at the data (D) input will not affect  
the output information any other time due to the master-slave construction of  
this device.  
L SUFFIX  
CERAMIC PACKAGE  
CASE 620–10  
P
= 460 mW typ/pkg (No Load)  
= 150 MHz (typ)  
D
f
toggle  
t , t = 2.0 ns typ (20%–80%)  
r f  
P SUFFIX  
PLASTIC PACKAGE  
CASE 648–08  
LOGIC DIAGRAM  
FN SUFFIX  
PLCC  
CASE 775–02  
D0  
D1  
5
6
2
Q0  
Q1  
DIP  
3
PIN ASSIGNMENT  
V
V
CC2  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
CC1  
D2  
D3  
D4  
D5  
7
10  
11  
12  
4
Q2  
Q5  
Q0  
Q4  
Q1  
Q2  
D0  
D1  
D2  
Q3  
13 Q3  
14 Q4  
15 Q5  
D5  
D4  
D3  
V
CLOCK  
EE  
Pin assignment is for Dual–in–Line Package.  
For PLCC pin assignment, see the Pin Conversion  
Tables on page 6–11 of the Motorola MECL Data  
Book (DL122/D).  
CLOCK  
9
V
V
= PIN 1  
= PIN 16  
= PIN 8  
CC1  
CC2  
V
EE  
CLOCKED TRUTH TABLE  
C
D
X
L
Q
n+1  
L
Q
n
H*  
H*  
L
H
H
*A clock H is a clock transition  
from a low to a high state.  
3/93  
Motorola, Inc. 1996  
REV 5  

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