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MC10178 PDF预览

MC10178

更新时间: 2024-11-03 22:54:59
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安森美 - ONSEMI 计数器
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5页 113K
描述
Binary Counter

MC10178 数据手册

 浏览型号MC10178的Datasheet PDF文件第2页浏览型号MC10178的Datasheet PDF文件第3页浏览型号MC10178的Datasheet PDF文件第4页浏览型号MC10178的Datasheet PDF文件第5页 
SEMICONDUCTOR TECHNICAL DATA  
The MC10178 is a four–bit counter capable of divide–by–two,  
divide–by–four, divide–by–eight or a divide–by–sixteen function.  
Clock inputs trigger on the positive going edge of the clock pulse. Set and  
Reset inputs override the clock, allowing asynchronous “set” or “clear.”  
Individual Set and common Reset inputs are provided, as well as  
complementary outputs for the first and fourth bits. True outputs are available at  
all bits.  
L SUFFIX  
CERAMIC PACKAGE  
CASE 620–10  
P
= 370 mW typ/pkg (No Load)  
= 150 MHz (typ)  
D
f
toggle  
t , t = 2.7 ns typ (20%–80%)  
r f  
P SUFFIX  
PLASTIC PACKAGE  
CASE 648–08  
LOGIC DIAGRAM  
FN SUFFIX  
PLCC  
S0  
Q0  
S1  
Q1  
S2  
Q2  
S3  
Q3  
11  
15  
7
13  
6
4
5
2
CASE 775–02  
S
R
S
R
S
R
S
R
D1  
C1  
Q’  
Q’  
D1  
C1  
Q’  
Q’  
D1  
C1  
Q’  
Q’  
D1  
C1  
Q’  
Q
12  
10  
Clock 1  
Clock 2  
DIP  
PIN ASSIGNMENT  
C2  
Q
Q
Q
Q
Q
9
V
V
CC2  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
Reset  
CC1  
14  
3
Q0  
Q3  
Q0  
Q3  
V
V
V
= PIN 1  
= PIN 16  
= PIN 8  
CC1  
CC2  
EE  
Q3  
Q2  
S3  
S2  
S1  
Q0  
Q1  
CLOCK 1  
S0  
TRUTH TABLE  
INPUTS  
S2  
OUTPUTS  
CLOCK 2  
RESET  
R
S0  
S1  
S3  
C1  
C2  
Q0  
Q1  
Q2  
Q3  
H
L
L
H
L
H
L
H
L
H
X
X
X
X
L
H
L
H
L
H
L
H
V
EE  
L
L
L
L
L
L
L
L
L
L
H
X
X
H
No Count  
No Count  
Pin assignment is for Dual–in–Line Package.  
For PLCC pin assignment, see the Pin Conversion  
Tables on page 6–11 of the Motorola MECL Data  
Book (DL122/D).  
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
**  
**  
**  
**  
**  
**  
**  
**  
**  
**  
**  
**  
**  
**  
**  
**  
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
L
L
L
H
H
H
H
L
L
H
H
L
L
L
H
H
L
L
H
H
L
L
H
H
H
H
**  
V
V
Clock transition from V to V may be applied to C or C or both for  
same effect.  
IH  
IL  
IH  
1
2
IL  
3/93  
Motorola, Inc. 1996  
REV 5  

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