Datasheet > 逻辑 > 计数器> MC100E137FN

MC100E137FN

更新时间： 2024-11-19 04:15:47

品牌	Logo	应用领域
安森美 - ONSEMI		计数器触发器逻辑集成电路输出元件输入元件
页数	文件大小	规格书
9页	139K
描述
5 V ECL 8-Bit Ripple Counter

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技术参数
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MC100E137FN 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	QLCC	包装说明：	QCCJ, LDCC28,.5SQ
针数：	28	Reach Compliance Code：	not_compliant
HTS代码：	8542.39.00.01	风险等级：	7.53
Is Samacsys：	N	Base Number Matches：	1

MC100E137FN 数据手册

MC10E137, MC100E137

5 VꢀECL 8-Bit Ripple Counter

Description

The MC10E/100E137 is a very high speed binary ripple counter. The

two least significant bits were designed with very fast edge rates while

the more significant bits maintain standard ECLinPS™ output edge

rates. This allows the counter to operate at very high frequencies while

maintaining a moderate power dissipation level.

http://onsemi.com

The device is ideally suited for multiple frequency clock generation

as well as a counter in a high performance ATE time measurement

board.

Both asynchronous and synchronous enables are available to

maximize the device’s flexibility for various applications. The

asynchronous enable input, A_Start, when asserted enables the counter

while overriding any synchronous enable signals. The E137 features

XORed enable inputs, EN1 and EN2, which are synchronous to the

CLK input. When only one synchronous enable is asserted the counter

becomes disabled on the next CLK transition; all outputs remain in the

previous state poised for the other synchronous enable or A_Start to be

asserted to re-enable the counter. Asserting both synchronous enables

causes the counter to become enabled on the next transition of the CLK.

If EN1 (or EN2) and CLK edges are coincident, sufficient delay has

been inserted in the CLK path (to compensate for the XOR gate delay

and the internal D-flip flop setup time) to insure that the synchronous

enable signal is clocked correctly, hence, the counter is disabled.

All input pins left open will be pulled LOW via an input pulldown

resistor. Therefore, do not leave the differential CLK inputs open.

Doing so causes the current source transistor of the input clock gate to

become saturated, thus upsetting the internal bias regulators and

jeopardizing the stability of the device.

PLCC−28

FN SUFFIX

CASE 776

MARKING DIAGRAM*

MCxxxE137FNG

AWLYYWW

xxx

= 10 or 100

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb−Free Package

The asynchronous Master Reset resets the counter to an all zero state

upon assertion.

The V pin, an internally generated voltage supply, is available to

*For additional marking information, refer to

Application Note AND8002/D.

this device only. For single-ended input conditions, the unused

differential input is connected to V as a switching reference voltage.

may also rebias AC coupled inputs. When used, decouple V and

via a 0.01 mF capacitor and limit current sourcing or sinking to

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 7 of this data sheet.

0.5 mA. When not used, V should be left open.

The 100 Series contains temperature compensation.

Features

• Differential Clock Input and Data Output Pins

• ESD Protection: Human Body Model: > 2 kV,

Machine Model: > 200 V

• Meets or Exceeds JEDEC Spec EIA/JESD78 IC

Latchup Test

• Moisture Sensitivity Level: Pb = 1; Pb−Free = 3

For Additional Information, see Application Note

AND8003/D

• Flammability Rating: UL 94 V−0 @ 0.125 in,

Oxygen Index: 28 to 34

• V Output for Single-Ended Use

• Synchronous and Asynchronous Enable Pins

• Asynchronous Master Reset

• PECL Mode Operating Range: V = 4.2 V to 5.7 V

with V = 0 V

• NECL Mode Operating Range: V = 0 V

with V = −4.2 V to −5.7 V

• Internal Input 50 kW Pull−down Resistors

• Transistor Count = 330 devices

• Pb−Free Packages are Available*

*For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting

Techniques Reference Manual, SOLDERRM/D.

Semiconductor Components Industries, LLC, 2006

Publication Order Number:

November, 2006 − Rev. 8

MC10E137/D

12 3 4 5 6 7...9

中文翻译

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MC100E137FN 替代型号

型号	品牌	替代类型	描述	数据表
MC100E137FNR2G	ONSEMI	完全替代	5 V ECL 8-Bit Ripple Counter
MC10E137FNR2G	ONSEMI	类似代替	5 V ECL 8-Bit Ripple Counter
MC10E137FNG	ONSEMI	功能相似	5 V ECL 8-Bit Ripple Counter

与MC100E137FN相关器件

型号	品牌	获取价格	描述	数据表
MC100E137FNG	ONSEMI	获取价格	5 V ECL 8-Bit Ripple Counter
MC100E137FNR2	ONSEMI	获取价格	5 V ECL 8-Bit Ripple Counter
MC100E137FNR2G	ONSEMI	获取价格	5 V ECL 8-Bit Ripple Counter
MC100E141	ONSEMI	获取价格	8-BIT SHIFT REGISTER
MC100E141FN	MOTOROLA	获取价格	8-BIT SHIFT REGISTER
MC100E141FN	ONSEMI	获取价格	5V ECL 8-Bit Shift Register
MC100E141FNG	ONSEMI	获取价格	5V ECL 8-Bit Shift Register
MC100E141FNR2	ONSEMI	获取价格	5V ECL 8-Bit Shift Register
MC100E141FNR2G	ONSEMI	获取价格	5V ECL 8-Bit Shift Register
MC100E142	ONSEMI	获取价格	9-BIT SHIFT REGISTER

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