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MC-4564EC727PF-A75 PDF预览

MC-4564EC727PF-A75

更新时间: 2024-01-08 16:19:34
品牌 Logo 应用领域
日电电子 - NEC 内存集成电路动态存储器时钟
页数 文件大小 规格书
16页 183K
描述
64M-WORD BY 72-BIT SYNCHRONOUS DYNAMIC RAM MODULE REGISTERED TYPE

MC-4564EC727PF-A75 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:DIMM包装说明:DIMM, DIMM168
针数:168Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.36
风险等级:5.92Is Samacsys:N
访问模式:FOUR BANK PAGE BURST最长访问时间:5.4 ns
其他特性:AUTO/SELF REFRESH最大时钟频率 (fCLK):133 MHz
I/O 类型:COMMONJESD-30 代码:R-XDMA-N168
内存密度:4831838208 bit内存集成电路类型:SYNCHRONOUS DRAM MODULE
内存宽度:72湿度敏感等级:1
功能数量:1端口数量:1
端子数量:168字数:67108864 words
字数代码:64000000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:64MX72输出特性:3-STATE
封装主体材料:UNSPECIFIED封装代码:DIMM
封装等效代码:DIMM168封装形状:RECTANGULAR
封装形式:MICROELECTRONIC ASSEMBLY峰值回流温度(摄氏度):225
电源:3.3 V认证状态:Not Qualified
刷新周期:4096自我刷新:YES
最大待机电流:0.116 A子类别:DRAMs
最大压摆率:5.26 mA最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:NO技术:CMOS
温度等级:COMMERCIAL端子形式:NO LEAD
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIEDBase Number Matches:1

MC-4564EC727PF-A75 数据手册

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DATA SHEET  
MOS INTEGRATED CIRCUIT  
MC-4564EC727  
64M-WORD BY 72-BIT SYNCHRONOUS DYNAMIC RAM MODULE  
REGISTERED TYPE  
Description  
The MC-4564EC727 is a 67,108,864 words by 72 bits synchronous dynamic RAM module on which 36 pieces of  
128 M SDRAM: µPD45128441 are assembled.  
This module provides high density and large quantities of memory in a small space without utilizing the surface-  
mounting technology on the printed circuit board.  
Decoupling capacitors are mounted on power supply line for noise reduction.  
Features  
67,108,864 words by 72 bits organization (ECC type)  
Clock frequency and access time from CLK  
Clock frequency  
(MAX.)  
Access time from CLK  
(MAX.)  
Part number  
/CAS latency  
Module type  
MC-4564EC727EF-A75  
CL = 3  
CL = 2  
CL = 3  
CL = 2  
133 MHz  
100 MHz  
133 MHz  
100 MHz  
5.4 ns  
6.0 ns  
5.4 ns  
6.0 ns  
PC133 Registered DIMM  
Rev. 1.0 Compliant  
MC-4564EC727PF-A75  
Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge  
Pulsed interface  
Possible to assert random column address in every cycle  
Quad internal banks controlled by BA0 and BA1 (Bank Select)  
Programmable burst-length (1, 2, 4, 8 and Full Page)  
Programmable wrap sequence (Sequential / Interleave)  
Programmable /CAS latency (2, 3)  
Automatic precharge and controlled precharge  
CBR (Auto) refresh and self refresh  
All DQs have 10 Ω ± 10 % of series resistor  
Single 3.3 V ±0.3 V power supply  
LVTTL compatible  
4,096 refresh cycles/64 ms  
Burst termination by Burst Stop command and Precharge command  
168-pin dual in-line memory module (Pin pitch = 1.27 mm)  
Registered type  
Serial PD  
Stacked monolithic technology  
The information in this document is subject to change without notice. Before using this document, please  
confirm that this is the latest version.  
Not all devices/types available in every country. Please check with local NEC representative for  
availability and additional information.  
1999  
©
Document No.  
Date Published February 2000 NS CP(K)  
Printed in Japan  
M14461EJ2V0DS00 (2nd edition)  
The mark shows major revised points.  

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