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MC-4516DA726PFC-A80 PDF预览

MC-4516DA726PFC-A80

更新时间: 2024-11-18 11:11:15
品牌 Logo 应用领域
尔必达 - ELPIDA /
页数 文件大小 规格书
16页 171K
描述
16 M-WORD BY 72-BIT SYNCHRONOUS DYNAMIC RAM MODULE REGISTERED TYPE

MC-4516DA726PFC-A80 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:DIMM包装说明:DIMM, DIMM168
针数:168Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.36
风险等级:5.78访问模式:FOUR BANK PAGE BURST
最长访问时间:6 ns其他特性:AUTO/SELF REFRESH
最大时钟频率 (fCLK):125 MHzI/O 类型:COMMON
JESD-30 代码:R-XDMA-N168内存密度:1207959552 bit
内存集成电路类型:SYNCHRONOUS DRAM MODULE内存宽度:72
功能数量:1端口数量:1
端子数量:168字数:16777216 words
字数代码:16000000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:16MX72输出特性:3-STATE
封装主体材料:UNSPECIFIED封装代码:DIMM
封装等效代码:DIMM168封装形状:RECTANGULAR
封装形式:MICROELECTRONIC ASSEMBLY电源:3.3 V
认证状态:Not Qualified刷新周期:4096
自我刷新:YES最大待机电流:0.089 A
子类别:DRAMs最大压摆率:2.37 mA
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:NO
技术:CMOS温度等级:COMMERCIAL
端子形式:NO LEAD端子节距:1.27 mm
端子位置:DUALBase Number Matches:1

MC-4516DA726PFC-A80 数据手册

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DATA SHEET  
MOS INTEGRATED CIRCUIT  
MC-4516DA726  
16 M-WORD BY 72-BIT SYNCHRONOUS DYNAMIC RAM MODULE  
REGISTERED TYPE  
Description  
The MC-4516DA726 is a 16,777,216 words by 72 bits synchronous dynamic RAM module on which 9 pieces of  
128M SDRAM: µPD45128841 are assembled.  
These modules provide high density and large quantities of memory in a small space without utilizing the surface-  
mounting technology on the printed circuit board.  
Decoupling capacitors are mounted on power supply line for noise reduction.  
Features  
16,777,216 words by 72 bits organization (ECC type)  
Clock frequency and access time from CLK  
Part number  
/CAS latency  
Clock frequency  
(MAX.)  
Access time from CLK  
(MAX.)  
Module type  
MC-4516DA726EFC-A80  
MC-4516DA726EFC-A10  
MC-4516DA726PFC-A80  
MC-4516DA726PFC-A10  
MC-4516DA726XFC-A80  
MC-4516DA726XFC-A10  
CL = 3  
CL = 2  
CL = 3  
CL = 2  
CL = 3  
CL = 2  
CL = 3  
CL = 2  
CL = 3  
CL = 2  
CL = 3  
CL = 2  
125 MHz  
100 MHz  
100 MHz  
77 MHz  
6 ns  
6 ns  
6 ns  
7 ns  
6 ns  
6 ns  
6 ns  
7 ns  
6 ns  
6 ns  
6 ns  
7 ns  
PC100 Registered DIMM  
Rev. 1.2 Compliant  
125 MHz  
100 MHz  
100 MHz  
77 MHz  
125 MHz  
100 MHz  
100 MHz  
77 MHz  
Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge  
Pulsed interface  
Possible to assert random column address in every cycle  
Quad internal banks controlled by BA0 and BA1 (Bank Select)  
Programmable burst-length (1, 2, 4, 8 and Full Page)  
Programmable wrap sequence (Sequential / Interleave)  
Programmable /CAS latency (2, 3)  
The information in this document is subject to change without notice. Before using this document, please  
confirm that this is the latest version.  
Not all devices/types available in every country. Please check with local Elpida Memory, Inc. for  
availability and additional information.  
Document No. E0074N10 (1st edition)  
This product became EOL in March, 2004.  
(Previous No. M13203EJ8V0DS00)  
Date Published January 2001 CP(K)  
Printed in Japan  
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.  

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