Datasheet > MB86943BPB

MB86943BPB

更新时间： 2024-11-29 19:55:27

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MB86943BPB 技术参数

FUJITSU SEMICONDUCTOR

DATA SHEET

DS07-05604-1E

Microprocessor SPARClite

CMOS

Peripherals for SPARClite

MB86943B

■ DESCRIPTION

The MB86943B is a bus bridge that allows high-speed [data] transfers between the host processor (SPARClite*

Family) and the PCI-bus. This bridge chip enables SPARClite (host CPU) access in program mode (direct master

operation) to devices on a PCI bus. Also, the SPARClite host can invoke the built-in DMA function on the bridge

chip to allow access to devices on the PCI bus. Access from the PCI side to devices on the SPARClite bus (SL

bus) is enabled by using the bridge chip slave operation function. The DMA function can be started up from the

SL-bus side. The MB86943B supports Door Bell functions and Mail Box function as well.

* : SPARClite is a trademark of SPARC International, Inc. in the United States.

Fujitsu Microelectronics, Inc. has been granted permission to use the trademark.

■ FEATURES

Key hardware features

• Functions for SL-bus to PCI slave (possible to work in program mode)

• Functions for PCI-bus to SL-bus slave (possible to work in program mode)

• Two-channel DMA functions (between the SL-bus and the PCI-bus)

• Functions to access the SL-bus’s external areas (ECS0 through ECS2)

• Interrupt communication functions between the SL-bus and the PCI-bus by use of Door Bell and Mail Box.

(Continued)

■ PACKAGE

352-pin Plastic BGA

(BGA-352P-M03)

12 3 4 5 6 7...32

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