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MAX7312AWG

更新时间： 2024-02-04 17:51:22
品牌 Logo 应用领域
美信 - MAXIM /
页数 文件大小 规格书
17页 373K
描述
2-Wire-Interfaced 16-Bit I/O Port Expander with Interrupt and Hot-Insertion Protection

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中文翻译

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MAX7312AWG 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active包装说明：,
Reach Compliance Code：compliantFactory Lead Time：6 weeks
风险等级：5.72峰值回流温度（摄氏度）：NOT SPECIFIED
处于峰值回流温度下的最长时间：NOT SPECIFIEDuPs/uCs/外围集成电路类型：PARALLEL IO PORT, GENERAL PURPOSE
Base Number Matches：1

MAX7312AWG 数据手册

 浏览型号MAX7312AWG的Datasheet PDF文件第6页浏览型号MAX7312AWG的Datasheet PDF文件第7页浏览型号MAX7312AWG的Datasheet PDF文件第8页浏览型号MAX7312AWG的Datasheet PDF文件第10页浏览型号MAX7312AWG的Datasheet PDF文件第11页浏览型号MAX7312AWG的Datasheet PDF文件第12页 
2-Wire-Interfaced 16-Bit I/O Port Expander  
with Interrupt and Hot-Insertion Protection  
Eight of the MAX7312’s nine registers are configured to  
operate as four register pairs: input ports, output ports,  
polarity inversion ports, and configuration ports. After  
sending 1 byte of data to one register, the next byte is  
sent to the other register in the pair. For example, if the  
first byte of data is sent to output port 2, then the next  
byte of data is stored in output port 1. An unlimited  
number of data bytes can be sent in one write transmis-  
sion. This allows each ±-bit register to be updated inde-  
pendently of the other registers.  
Reading Port Registers  
To read the device data, the bus master must first send  
the MAX7312 address with the R/W bit set to zero, fol-  
lowed by the command byte, which determines which  
register is accessed. After a restart, the bus master  
must then send the MAX7312 address with the R/W bit  
set to 1. Data from the register defined by the com-  
mand byte is then sent from the MAX7312 to the master  
(Figures ±, 9).  
ACKNOWLEDGE  
FROM SLAVE  
DATA FROM LOWER OR  
UPPER BYTE OF REGISTER  
DATA FROM LOWER OR  
UPPER BYTE OF REGISTER  
S
SLAVE ADDRESS  
0
A
COMMAND BYTE  
A
S
SLAVE ADDRESS  
1
A
MSB  
DATA  
LSB  
A
MSB  
DATA  
LSB NA  
P
ACKNOWLEDGE  
FROM SLAVE  
R/W  
R/W  
ACKNOWLEDGE  
FROM SLAVE  
MASTER TRANSMITTER BECOMES  
MASTER RECEIVER AND SLAVE  
RECEIVER BECOMES SLAVE TRANSMITTER  
TRANSFER OF DATA CAN BE STOPPED AT ANY TIME BY A STOP CONDITION.  
Figure 8. Read from Register  
SCL  
1
2
3
4
5
6
7
8
9
S
SLAVE ADDRESS  
R/W  
1
A
7
PORT 1 DATA  
0
A
7
PORT 2 DATA  
0
A
7
PORT 1 DATA  
0
A
7
PORT 2 DATA  
0
1
P
ACKNOWLEDGE  
FROM SLAVE  
ACKNOWLEDGE  
FROM MASTER  
ACKNOWLEDGE  
FROM MASTER  
ACKNOWLEDGE  
FROM MASTER  
NONACKNOWLEDGE  
FROM MASTER  
READ FROM PORT 1  
DATA INTO PORT 1  
READ FROM PORT 2  
DATA INTO PORT 2  
INT  
t
t
IR  
IV  
TRANSFER OF DATA CAN BE STOPPED ANYTIME BY A STOP CONDITION. WHEN THE  
STOP CONDITION OCCURS, DATA PRESENT AT THE LAST ACKNOWLEDGE PHASE IS  
VALID (OUTPUT MODE) AND COMMAND BYTE HAS PREVIOUSLY BEEN SET TO REGISTER 00.  
Figure 9. Read from Input Registers  
_______________________________________________________________________________________  
9
1...6789101112...17

中文翻译

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MAX7313AEG MAXIM

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 		Parallel I/O Port, 1-Bit, 16 I/O, BICMOS, PDSO24, 0.150 INCH, 0.025 INCH PITCH, MO-137AE,
MAX7313AEG+T MAXIM

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 		Parallel I/O Port, 1-Bit, 16 I/O, BICMOS, PDSO24, 0.150 INCH, 0.025 INCH PITCH, MO-137AE,
MAX7313AEG-T MAXIM

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 		Parallel I/O Port, 1-Bit, 16 I/O, BICMOS, PDSO24, 0.150 INCH, 0.025 INCH PITCH, MO-137AE,
MAX7313ATG MAXIM

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 		16-Port I/O Expander with LED Intensity Control, Interrupt, and Hot-Insertion Protection
MAX7313ATG+ MAXIM

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 		Parallel I/O Port, 1-Bit, 16 I/O, BICMOS, 4 X 4 MM, 0.80 MM PITCH, MO-220WGGD-2, TQFN-24

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