19-6185; Rev 0; 2/12
MAX5823/MAX5824/MAX5825
Ultra-Small, Octal Channel, 8-/10-/12-Bit Buffered
2
Output DACs with Internal Reference and I C Interface
General Description
Benefits and Features
S Eight High-Accuracy DAC Channels
The MAX5823/MAX5824/MAX5825 8-channel, low-power,
8-/10-/12-bit, voltage-output digital-to-analog converters
(DACs) include output buffers and an internal 3ppm/°C
reference that is selectable to be 2.048V, 2.500V, or
4.096V. The MAX5823/MAX5824/MAX5825 accept a
wide supply voltage range of 2.7V to 5.5V with extremely
low power (6mW) consumption to accommodate most
low-voltage applications. A precision external reference
input allows rail-to-rail operation and presents a 100kI
(typ) load to an external reference.
TheMAX5823/MAX5824/MAX5825haveanI2C-compatible,
2-wire interface that operates at clock rates up to
400kHz. The DAC output is buffered and has a low sup-
ply current of less than 250FA per channel and a low
offset error of Q0.5mV (typ). On power-up, the MAX5823/
MAX5824/MAX5825 reset the DAC outputs to zero or mid-
scale based on the status of M/Z logic input, providing
flexibility for a variety of control applications. The internal
reference is initially powered down to allow use of an
external reference. The MAX5823/MAX5824/MAX5825
allow simultaneous output updates using software LOAD
commands or the hardware load DAC logic input (LDAC).
12-Bit Accuracy Without Adjustment
ꢀ1 ꢁLB ꢂIꢁ Buꢃꢃered ꢄoltage ꢅutꢆut
ꢀGuaranteed Monotonic ꢅver All ꢅꢆerating
Conditions
ꢀꢂndeꢆendent Mode Lettings ꢃor Each DAC
S Three Precision Lelectable ꢂnternal Reꢃerences
ꢀ2.048ꢄ, 2.500ꢄ, or 4.096ꢄ
S ꢂnternal ꢅutꢆut Buꢃꢃer
ꢀRail-to-Rail ꢅꢆeration with External Reꢃerence
4.5µs Lettling Time
ꢅutꢆuts Directly Drive 2kI ꢁoads
S Lmall 6.5mm x 4.4mm 20-Pin TLLꢅP or Ultra-
Lmall 2.5mm x 2.3mm 20-Bumꢆ WꢁP Package
S Wide 2.7ꢄ to 5.5ꢄ Luꢆꢆly Range
S Leꢆarate 1.8ꢄ to 5.5ꢄ ꢄ
Power-Luꢆꢆly ꢂnꢆut
DDꢂꢅ
S Fast 400kHz ꢂ2C-Comꢆatible, 2-Wire Lerial
ꢂnterꢃace
S Pin-Lelectable Power-ꢅn-Reset to Zero-Lcale or
Midscale DAC ꢅutꢆut
S LDAC and CLR For Asynchronous DAC Control
The MAX5823/MAX5824/MAX5825 feature a watchdog
function which can be enabled to monitor the I/O inter-
face for activity and integrity.
S Three Loꢃtware-Lelectable Power-Down ꢅutꢆut
ꢂmꢆedances
ꢀ1kI, 100kI, or High ꢂmꢆedance
A clear logic input (CLR) allows the contents of the CODE
and the DAC registers to be cleared asynchronously and
simultaneously sets the DAC outputs to the program-
mable default value. The MAX5823/MAX5824/MAX5825
are available in a 20-pin TSSOP and an ultra-small,
20-bump WLP package and are specified over the -40NC
to +125NC temperature range.
Functional Diagram
V
V
REF
DDIO
DD
MAX5823
MAX5824
MAX5825
INTERNAL REFERENCE/
EXTERNAL BUFFER
SCL
SDA
1 OF 8 DAC CHANNELS
Applications
ADDR0
ADDR1
CODE
REGISTER
DAC
LATCH
8-/10-/12-BIT
DAC
2
C SERIAL
I
INTERFACE
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
BUFFER
Programmable Voltage and Current Sources
Gain and Offset Adjustment
CLR
LDAC
(GATE/
CLEAR/
RESET)
CLEAR/
RESET
CODE
LOAD
100kI
1kI
Automatic Tuning and Optical Control
Power Amplifier Control and Biasing
Process Control and Servo Loops
Portable Instrumentation
IRQ
WATCHDOG
TIMER
POWER-DOWN
DAC CONTROL LOGIC
M/Z
POR
GND
Ordering Information appears at end of data sheet.
For related parts and recommended products to use with this part, refer to: www.maxim-ic.com/MAX5823.related
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1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.