EVALUATION KIT AVAILABLE
MAX5823/MAX5824/MAX5825
Ultra-Small, Octal Channel, 8-/10-/12-Bit Buffered
2
Output DACs with Internal Reference and I C Interface
General Description
Benefits and Features
S Eight High-Accuracy DAC Channels
The MAX5823/MAX5824/MAX5825 8-channel, low-power,
8-/10-/12-bit, voltage-output digital-to-analog converters
(DACs) include output buffers and an internal 3ppm/°C
reference that is selectable to be 2.048V, 2.500V, or
4.096V. The MAX5823/MAX5824/MAX5825 accept a
wide supply voltage range of 2.7V to 5.5V with extremely
low power (6mW) consumption to accommodate most
low-voltage applications. A precision external reference
input allows rail-to-rail operation and presents a 100kI
(typ) load to an external reference.
TheMAX5823/MAX5824/MAX5825haveanI2C-compatible,
2-wire interface that operates at clock rates up to
400kHz. The DAC output is buffered and has a low sup-
ply current of less than 250FA per channel and a low
offset error of Q0.5mV (typ). On power-up, the MAX5823/
MAX5824/MAX5825 reset the DAC outputs to zero or mid-
scale based on the status of M/Z logic input, providing
flexibility for a variety of control applications. The internal
reference is initially powered down to allow use of an
external reference. The MAX5823/MAX5824/MAX5825
allow simultaneous output updates using software LOAD
commands or the hardware load DAC logic input (LDAC).
12-Bit Accuracy Without Adjustment
ꢀ1 ꢀLB ꢁIꢀ Buꢂꢂered ꢃoltage ꢄutꢅut
ꢀGuaranteed Monotonic ꢄver All ꢄꢅerating
Conditions
ꢀꢁndeꢅendent Mode Lettings ꢂor Each DAC
S Three Precision Lelectable ꢁnternal Reꢂerences
ꢀ2.048ꢃ, 2.500ꢃ, or 4.096ꢃ
S ꢁnternal ꢄutꢅut Buꢂꢂer
ꢀRail-to-Rail ꢄꢅeration with External Reꢂerence
4.5µs Lettling Time
ꢄutꢅuts Directly Drive 2kI ꢀoads
S Lmall 6.5mm x 4.4mm 20-Pin TLLꢄP or Ultra-
Lmall 2.5mm x 2.3mm 20-Bumꢅ WꢀP Package
S Wide 2.7ꢃ to 5.5ꢃ Luꢅꢅly Range
S Leꢅarate 1.8ꢃ to 5.5ꢃ ꢃ
Power-Luꢅꢅly ꢁnꢅut
DDꢁꢄ
S Fast 400kHz ꢁ2C-Comꢅatible, 2-Wire Lerial
ꢁnterꢂace
S Pin-Lelectable Power-ꢄn-Reset to Zero-Lcale or
Midscale DAC ꢄutꢅut
S LDAC and CLR For Asynchronous DAC Control
The MAX5823/MAX5824/MAX5825 feature a watchdog
function which can be enabled to monitor the I/O inter-
face for activity and integrity.
S Three Loꢂtware-Lelectable Power-Down ꢄutꢅut
ꢁmꢅedances
ꢀ1kI, 100kI, or High ꢁmꢅedance
A clear logic input (CLR) allows the contents of the CODE
and the DAC registers to be cleared asynchronously and
simultaneously sets the DAC outputs to the program-
mable default value. The MAX5823/MAX5824/MAX5825
are available in a 20-pin TSSOP and an ultra-small,
20-bump WLP package and are specified over the -40NC
to +125NC temperature range.
Functional Diagram
V
V
REF
DDIO
DD
MAX5823
MAX5824
MAX5825
INTERNAL REFERENCE/
EXTERNAL BUFFER
SCL
SDA
1 OF 8 DAC CHANNELS
BUFFER
Applications
ADDR0
ADDR1
CODE
REGISTER
DAC
LATCH
8-/10-/12-BIT
DAC
2
C SERIAL
I
INTERFACE
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
Programmable Voltage and Current Sources
Gain and Offset Adjustment
CLR
LDAC
(GATE/
CLEAR/
RESET)
CLEAR/
RESET
CODE
LOAD
100kI
1kI
Automatic Tuning and Optical Control
Power Amplifier Control and Biasing
Process Control and Servo Loops
Portable Instrumentation
IRQ
WATCHDOG
TIMER
POWER-DOWN
DAC CONTROL LOGIC
M/Z
POR
GND
Ordering Information appears at end of data sheet.
For related parts and recommended products to use with this part,
refer to: www.maximintegrated.com/MAX5823.related
For pricing, delivery, and ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.
19-6185; Rev 2; 2/13
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