MAX5823/MAX5824/
MAX5825
Ultra-Small, Octal Channel, 8-/10-/12-Bit
Buffered Output DACs with Internal
2
Reference and I C Interface
General Description
Benefits and Features
● Eight High-Accuracy DAC Channels
• 12-Bit Accuracy Without Adjustment
• ±1 LSB INL Buffered Voltage Output
• Guaranteed Monotonic Over All Operating
Conditions
The MAX5823/MAX5824/MAX5825 8-channel, low-power,
8-/10-/12-bit, voltage-output digital-to-analog converters
(DACs) include output buffers and an internal 3ppm/°C
reference that is selectable to be 2.048V, 2.500V, or
4.096V. The MAX5823/MAX5824/MAX5825 accept a
wide supply voltage range of 2.7V to 5.5V with extremely
low power (6mW) consumption to accommodate most
low-voltage applications. A precision external reference
input allows rail-to-rail operation and presents a 100kΩ
(typ) load to an external reference.
• Independent Mode Settings for Each DAC
● Three Precision Selectable Internal References
• 2.048V, 2.500V, or 4.096V
● Internal Output Buffer
• Rail-to-Rail Operation with External Reference
• 4.5µs Settling Time
2
The MAX5823/MAX5824/MAX5825 have an I C-
compatible, 2-wire interface that operates at clock rates
up to 400kHz. The DAC output is buffered and has a low
supply current of less than 250µA per channel and a low
offset error of ±0.5mV (typ). On power-up, the MAX5823/
MAX5824/MAX5825 reset the DAC outputs to zero or
mid-scale based on the status of M/Z logic input, providing
flexibility for a variety of control applications. The internal
reference is initially powered down to allow use of an
external reference. The MAX5823/MAX5824/MAX5825
allow simultaneous output updates using software LOAD
commands or the hardware load DAC logic input (LDAC).
• Outputs Directly Drive 2kΩ Loads
● Small 6.5mm x 4.4mm 20-Pin TSSOP or Ultra-Small
2.5mm x 2.3mm 20-Bump WLP Package
● Wide 2.7V to 5.5V Supply Range
● Separate 1.8V to 5.5V V
Power-Supply Input
DDIO
● Fast 400kHz I2C-Compatible, 2-Wire Serial Interface
● Pin-Selectable Power-On-Reset to Zero-Scale or
Midscale DAC Output
● LDAC and CLR For Asynchronous DAC Control
● Three Software-Selectable Power-Down Output
Impedances
The MAX5823/MAX5824/MAX5825 feature a watchdog
function which can be enabled to monitor the I/O interface
for activity and integrity.
• 1kΩ, 100kΩ, or High Impedance
A clear logic input (CLR) allows the contents of the CODE
and the DAC registers to be cleared asynchronously and
simultaneously sets the DAC outputs to the programmable
default value. The MAX5823/MAX5824/MAX5825 are
available in a 20-pin TSSOP and an ultra-small, 20-bump
WLP package and are specified over the -40°C to +125°C
temperature range.
Functional Diagram
V
V
REF
DDIO
DD
MAX5823
MAX5824
MAX5825
INTERNAL REFERENCE/
EXTERNAL BUFFER
SCL
SDA
1 OF 8 DAC CHANNELS
BUFFER
Applications
● Programmable Voltage and Current Sources
ADDR0
ADDR1
CODE
REGISTER
DAC
LATCH
8-/10-/12-BIT
DAC
2
C SERIAL
INTERFACE
I
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
CLR
● Gain and Offset Adjustment
LDAC
(GATE/
CLEAR/
RESET)
CLEAR/
RESET
CODE
LOAD
● Automatic Tuning and Optical Control
● Power Amplifier Control and Biasing
● Process Control and Servo Loops
● Portable Instrumentation
100kI
1kI
IRQ
WATCHDOG
TIMER
POWER-DOWN
DAC CONTROL LOGIC
M/Z
POR
GND
Ordering Information appears at end of data sheet.
19-6185; Rev 3; 8/19
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