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M76DW52003TA90Z PDF预览

M76DW52003TA90Z

更新时间: 2024-11-04 20:42:07
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 静态存储器内存集成电路
页数 文件大小 规格书
27页 389K
描述
SPECIALTY MEMORY CIRCUIT, PBGA73, 8 X 11.60 MM, 0.80 MM PITCH, LFBGA-73

M76DW52003TA90Z 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:BGA包装说明:8 X 11.60 MM, 0.80 MM PITCH, LFBGA-73
针数:73Reach Compliance Code:compliant
HTS代码:8542.32.00.71风险等级:5.92
最长访问时间:90 ns其他特性:STATIC RAM IS ORGANIZED AS 256K X 16; FLASH MEMORY IS ALSO ORGANIZED AS 4M X 8
JESD-30 代码:R-PBGA-B73JESD-609代码:e0
长度:11.6 mm内存密度:33554432 bit
内存集成电路类型:MEMORY CIRCUIT内存宽度:16
混合内存类型:FLASH+SRAM功能数量:1
端子数量:73字数:2097152 words
字数代码:2000000工作模式:ASYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:2MX16封装主体材料:PLASTIC/EPOXY
封装代码:LFBGA封装等效代码:BGA73,10X12,32
封装形状:RECTANGULAR封装形式:GRID ARRAY, LOW PROFILE, FINE PITCH
峰值回流温度(摄氏度):NOT SPECIFIED电源:3,3/3.3 V
认证状态:Not Qualified座面最大高度:1.4 mm
最大待机电流:0.0001 A子类别:Other Memory ICs
最大压摆率:0.02 mA最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):2.7 V标称供电电压 (Vsup):3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:TIN LEAD
端子形式:BALL端子节距:0.8 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:8 mmBase Number Matches:1

M76DW52003TA90Z 数据手册

 浏览型号M76DW52003TA90Z的Datasheet PDF文件第2页浏览型号M76DW52003TA90Z的Datasheet PDF文件第3页浏览型号M76DW52003TA90Z的Datasheet PDF文件第4页浏览型号M76DW52003TA90Z的Datasheet PDF文件第5页浏览型号M76DW52003TA90Z的Datasheet PDF文件第6页浏览型号M76DW52003TA90Z的Datasheet PDF文件第7页 
M76DW52003TA  
M76DW52003BA  
32Mbit (4Mb x8/ 2Mb x16, Dual Bank, Boot Block) Flash Memory  
and 4Mbit (256Kb x16) SRAM, Multiple Memory Product  
PRELIMINARY DATA  
FEATURES SUMMARY  
MULTIPLE MEMORY PRODUCT  
Figure 1. Package  
– 32 Mbit (4Mb x8 or 2Mb x16), Dual Bank, Boot  
Block, Flash Memory  
– 4 Mbit (256Kb x 16) SRAM  
SUPPLY VOLTAGE  
– V  
– V  
– V  
= 2.7V to 3.3V  
CCF  
CCS  
PPF  
= 2.7V to 3.3V  
FBGA  
= 12V for Fast Program (optional)  
ACCESS TIME: 70, 90ns  
LOW POWER CONSUMPTION  
ELECTRONIC SIGNATURE  
– Manufacturer Code: 0020h  
LFBGA73 (ZA)  
8 x 11.6 mm  
– Top Device Code, M76DW52003TA: 225Eh  
– Bottom Device Code, M76DW52003BA:  
225Fh  
FLASH MEMORY  
PROGRAMMING TIME  
– 10µs per Byte/Word typical  
– Double Word/ Quadruple Byte Program  
MEMORY BLOCKS  
EXTENDED MEMORY BLOCK  
– Extra block used as security block or to store  
additional information  
100,000 PROGRAM/ERASE CYCLES per  
– Dual Bank Memory Array: 8Mbit+24Mbit  
– Parameter Blocks (Top or Bottom Location)  
DUAL OPERATIONS  
BLOCK  
SRAM  
4 Mbit (256Kb x 16)  
– Read in one bank while Program or Erase in  
other  
ACCESS TIME: 70ns  
LOW V  
DATA RETENTION: 1.5V  
ERASE SUSPEND and RESUME MODES  
CCS  
POWER DOWN FEATURES USING TWO  
– Read and Program another Block during  
Erase Suspend  
CHIP ENABLE INPUTS  
UNLOCK BYPASS PROGRAM COMMAND  
– Faster Production/Batch Programming  
V /WP PIN for FAST PROGRAM and WRITE  
PP  
PROTECT  
TEMPORARY BLOCK UNPROTECTION  
MODE  
COMMON FLASH INTERFACE  
– 64 bit Security Code  
September 2003  
1/27  
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.  

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