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M74HC696TTR PDF预览

M74HC696TTR

更新时间: 2024-09-19 20:06:43
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 光电二极管逻辑集成电路触发器
页数 文件大小 规格书
16页 135K
描述
HC/UH SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL DECADE COUNTER, PDSO20, TSSOP-20

M74HC696TTR 技术参数

生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP,针数:20
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.84计数方向:BIDIRECTIONAL
系列:HC/UHJESD-30 代码:R-PDSO-G20
长度:6.5 mm负载/预设输入:YES
逻辑集成电路类型:DECADE COUNTER工作模式:SYNCHRONOUS
位数:4功能数量:1
端子数量:20最高工作温度:125 °C
最低工作温度:-55 °C输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
传播延迟(tpd):370 ns认证状态:Not Qualified
座面最大高度:1.2 mm最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):4.5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
触发器类型:POSITIVE EDGE宽度:4.4 mm
最小 fmax:20 MHzBase Number Matches:1

M74HC696TTR 数据手册

 浏览型号M74HC696TTR的Datasheet PDF文件第2页浏览型号M74HC696TTR的Datasheet PDF文件第3页浏览型号M74HC696TTR的Datasheet PDF文件第4页浏览型号M74HC696TTR的Datasheet PDF文件第5页浏览型号M74HC696TTR的Datasheet PDF文件第6页浏览型号M74HC696TTR的Datasheet PDF文件第7页 
M74HC696  
U/D DECADE COUNTER/REGISTER (3-STATE)  
HIGH SPEED:  
= 53 MHz (TYP.) at V = 6V  
f
MAX  
CC  
LOW POWER DISSIPATION:  
= 4µA(MAX.) at T =25°C  
I
CC  
A
HIGH NOISE IMMUNITY:  
= V = 28 % V (MIN.)  
V
NIH  
NIL  
CC  
DIP  
SOP  
TSSOP  
T & R  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 6mA (MIN) for Q to Q OUTPUT  
OH  
OL  
A
D
|I | = I = 4mA (MIN) for RCO OUTPUT  
OH  
OL  
BALANCED PROPAGATION DELAYS:  
ORDER CODES  
PACKAGE  
t
t
PLH  
PHL  
TUBE  
WIDE OPERATING VOLTAGE RANGE:  
(OPR) = 2V to 6V  
DIP  
SOP  
M74HC696B1R  
M74HC696M1R  
V
CC  
M74HC696RM13TR  
M74HC696TTR  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 696  
TSSOP  
DESCRIPTION  
The M74HC696 is an high speed CMOS UP /  
DOWN COUNTER REGISTER (3 STATE)  
fabricated with silicon gate C MOS technology.  
The M74HC696 is a BCD DECADE COUNTER  
with REGISTER.  
The device counts on the positive edge of the  
counter clock input (CCK) when selected by the  
”Counter Mode”. If the input U/D is held ”H”, the  
internal counter counts up, and held ”L”, counts  
down. The internal counter’s outputs are stored in  
the output register at the positive edge of register  
clock (RCK).  
The counter features enable P and enable T and a  
ripple-carry output for easy expansion. The  
register/counter select input, R/C, selects the  
counter when low or the register when high for the  
three state outputs, QA, QB, QC, and QD. Both  
the counter clock CCR and register clock RCK are  
positive-edge triggered. The counter clear CCLR  
is active low and is asynchronous.  
2
All inputs are equipped with protection circuits  
against static discharge and transient excess  
voltage.  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
July 2001  
1/16  

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