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M74HC643M1R PDF预览

M74HC643M1R

更新时间: 2024-11-07 22:15:15
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 总线收发器
页数 文件大小 规格书
11页 268K
描述
OCTAL BUS TRANSCEIVER 3-STATE: HC245 NON INVERTING HC640 INVERTING, HC643 INVERTING/NON INVERTING

M74HC643M1R 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP-20针数:20
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.63其他特性:INVERTED OUTPUTS PORT A TO B
控制类型:COMMON CONTROL计数方向:BIDIRECTIONAL
系列:HC/UHJESD-30 代码:R-PDSO-G20
JESD-609代码:e4长度:12.8 mm
负载电容(CL):150 pF逻辑集成电路类型:BUS TRANSCEIVER
最大I(ol):0.006 A位数:8
功能数量:1端口数量:2
端子数量:20最高工作温度:125 °C
最低工作温度:-55 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP20,.4
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TUBE峰值回流温度(摄氏度):NOT SPECIFIED
电源:2/6 VProp。Delay @ Nom-Sup:27 ns
传播延迟(tpd):180 ns认证状态:Not Qualified
座面最大高度:2.65 mm子类别:Bus Driver/Transceivers
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):4.5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED翻译:N/A
宽度:7.5 mm

M74HC643M1R 数据手册

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M54/74HC245/640/643  
M54/74HC245/640/643  
OCTAL BUS TRANSCEIVER (3-STATE): HC245 NON INVERTING  
HC640 INVERTING, HC643 INVERTING/NON INVERTING  
.
HIGH SPEED  
PD = 10 ns (TYP.) at VCC = 5V  
LOW POWER DISSIPATION  
ICC = 4 µA (MAX.) at TA = 25 oC  
HIGH NOISE IMMUNITY  
t
.
.
.
.
.
.
.
V
NIH = VINL = 28 % VCC (MIN.)  
OUTPUT DRIVE CAPABILITY  
15 LSTTL LOADS  
SYMMETRICAL OUTPUT IMPEDANCE  
|IOH| = IOL = 6 mA (MIN)  
BALANCED PROPAGATION DELAYS  
tPLH = tPHL  
WIDE OPERATING VOLTAGE RANGE  
VCC (OPR) = 2 V TO 6 V  
B1R  
F1R  
(Plastic Package)  
(Ceramic Package)  
M1R  
C1R  
(Micro Package)  
(Chip Carrier)  
PIN AND FUNCTION COMPATIBLE  
WITH 54/74LS245/640/643  
ORDER CODES :  
M54HCXXXF1R  
M74HCXXXM1R  
M74HCXXXB1R  
M74HCXXXC1R  
DESCRIPTION  
The M54/74HC245, HC640 and HC643 utilise  
silicon gate C2MOS technology to achive operating  
speeds equivalent to LSTTL devices.  
All input are equipped with protection circuits  
against staticdischarge and transient discharge and  
transient excess voltage.  
Along with the low power dissipation and high noise  
immunity of standards C2MOS integrated circuit, it  
possesses the capability to drive 15 LSTTL loads.  
These IC’s are intended for two-way asynchronous  
communication between data buses, and the  
direction of data trasmission is determined by DIR  
input. The enable input (G) can be used to disable  
the device so that the buses are effectively isolated.  
IT IS PROHIBITED TO APPLY A SIGNAL TO A  
BUS TERMINAL WHEN IT IS IN OUTPUT MODE  
AND WHEN A BUS THERMINAL IS FLOATING  
(HIGH IMPEDANCE STATE), IT IS REQUESTED  
TO FIX THE INPUT LEVEL BY MEANS OF  
EXTERNAL PULL DOWN OR PULL UP  
RESISTOR.  
PIN CONNECTION (top view)  
HC245  
HC640  
HC643  
October 1993  
1/11  

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