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M74HC648TTR PDF预览

M74HC648TTR

更新时间: 2024-11-29 13:10:11
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 总线收发器
页数 文件大小 规格书
12页 204K
描述
HC/UH SERIES, 8-BIT REGISTERED TRANSCEIVER, INVERTED OUTPUT, PDSO24, TSSOP-24

M74HC648TTR 技术参数

生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP-24针数:24
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.84Is Samacsys:N
控制类型:INDEPENDENT CONTROL计数方向:BIDIRECTIONAL
系列:HC/UHJESD-30 代码:R-PDSO-G24
长度:7.8 mm逻辑集成电路类型:REGISTERED BUS TRANSCEIVER
最大I(ol):0.006 A位数:8
功能数量:1端口数量:2
端子数量:24最高工作温度:125 °C
最低工作温度:-55 °C输出特性:3-STATE
输出极性:INVERTED封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP24,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法:TAPE AND REEL电源:2/6 V
Prop。Delay @ Nom-Sup:60 ns传播延迟(tpd):325 ns
认证状态:Not Qualified座面最大高度:1.2 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):4.5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
翻译:N/A触发器类型:POSITIVE EDGE
宽度:4.4 mmBase Number Matches:1

M74HC648TTR 数据手册

 浏览型号M74HC648TTR的Datasheet PDF文件第2页浏览型号M74HC648TTR的Datasheet PDF文件第3页浏览型号M74HC648TTR的Datasheet PDF文件第4页浏览型号M74HC648TTR的Datasheet PDF文件第5页浏览型号M74HC648TTR的Datasheet PDF文件第6页浏览型号M74HC648TTR的Datasheet PDF文件第7页 
M74HC646  
M74HC648  
HC646 OCTAL BUS TRANSCEIVER/REGISTER (3-STATE)  
HC648 OCTAL BUS TRANSCEIVER/REGISTER (3-STATE, INV.)  
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HIGH SPEED  
fMAX = 73 MHz (TYP.) AT VCC = 5 V  
LOW POWER DISSIPATION  
ICC = 4 µA (MAX.) AT TA = 25 °C  
HIGH NOISE IMMUNITY  
VNIH = VNIL = 28 % VCC (MIN.)  
OUTPUT DRIVE CAPABILITY  
15 LSTTL LOADS  
SYMMETRICAL OUTPUT IMPEDANCE  
IOH = IOL = 6 mA (MIN.)  
BALANCED PROPAGATION DELAYS  
tPLH = tPHL  
WIDE OPERATING VOLTAGE RANGE  
B1R  
(Plastic Package)  
M1R  
(Micro Package)  
ORDER CODES :  
M74HCXXXM1R  
M74HCXXXB1R  
VCC (OPR) = 2 V TO 6 V  
PIN AND FUNCTION COMPATIBLE  
WITH 54/74LS646/648  
DESCRIPTION  
PIN CONNECTIONS (top view)  
The M74HC646/648 are high speed CMOS OCTAL  
BUS TRANSCEIVERS AND REGISTERS, (3-  
STATE) fabricated in silicon gate C2MOS technol-  
ogy. They have the same high speed performance  
of LSTTL combined with trueCMOS low power con-  
sumption.  
These devices consist of bus transceiver circuits  
with 3-state output, D-type flip-flops, and control cir-  
cuitry arranged for multiplexed transmission of data  
directly from the input bus or from the internal reg-  
isters. Data on the Aor B bus will be clocked into the  
registers on the low-to-high transition of the appro-  
priate clock pin (Clock AB- or Clock BA). Enable(G)  
and direction (DIR) pins are provided to control the  
transceiver functions. In the transceiver mode, data  
present at the high-impedance port may be stored  
in either register or in both.  
INPUT AND OUTPUT EQUIVALENT CIRCUIT  
The select controls (Select AB select BA) can multi-  
plex stored and real-time (transparent mode) data.  
The direction control determines which bus will re-  
ceive data when enable G is active (low).  
GAB, GAB, CAB,  
SAB, SBA, CBA  
A, B  
In the isolation mode (enable G high), ”A” data may  
be stored in one register and/or ”B” data may be  
storedin the other register. When anoutput function  
is disabled, the input function is still enabled and  
may be used to store and transmit data. Only one  
of the two buses, A or B, may be driven at a time.  
All inputs are equipped with protection circuits  
October 1993  
1/12  

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