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M74HC651B1N PDF预览

M74HC651B1N

更新时间: 2024-11-29 13:10:11
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 总线收发器
页数 文件大小 规格书
12页 204K
描述
HC/UH SERIES, 8-BIT REGISTERED TRANSCEIVER, INVERTED OUTPUT, PDIP24, PLASTIC, DIP-24

M74HC651B1N 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:DIP
包装说明:DIP, DIP24,.3针数:24
Reach Compliance Code:not_compliant风险等级:5.92
其他特性:SELECT INPUT FOR MULTIPLEXED TRANSMISSION OF REGISTERED/REAL TIME DATA控制类型:INDEPENDENT CONTROL
计数方向:BIDIRECTIONAL系列:HC/UH
JESD-30 代码:R-PDIP-T24JESD-609代码:e0
负载电容(CL):50 pF逻辑集成电路类型:REGISTERED BUS TRANSCEIVER
最大I(ol):0.006 A位数:8
功能数量:1端口数量:2
端子数量:24最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:INVERTED封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP24,.3
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
Prop。Delay @ Nom-Sup:60 ns传播延迟(tpd):60 ns
认证状态:Not Qualified座面最大高度:3.93 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
翻译:N/A触发器类型:POSITIVE EDGE
宽度:10.16 mmBase Number Matches:1

M74HC651B1N 数据手册

 浏览型号M74HC651B1N的Datasheet PDF文件第2页浏览型号M74HC651B1N的Datasheet PDF文件第3页浏览型号M74HC651B1N的Datasheet PDF文件第4页浏览型号M74HC651B1N的Datasheet PDF文件第5页浏览型号M74HC651B1N的Datasheet PDF文件第6页浏览型号M74HC651B1N的Datasheet PDF文件第7页 
M74HC651  
M74HC652  
HC651 OCTAL BUS TRANSCEIVER/REGISTER (3-STATE, INV.)  
HC652 OCTAL BUS TRANSCEIVER/REGISTER (3-STATE)  
.
HIGH SPEED  
fMAX = 73 MHz (TYP.) AT VCC = 5V  
LOW POWER DISSIPATION  
ICC = 4 µA (MAX.) AT TA = 25 °C  
HIGH NOISE IMMUNITY  
VNIH = VNIL = 28 % VCC (MIN.)  
OUTPUT DRIVE CAPABILITY  
15 LSTTL LOADS  
SYMMETRICAL OUTPUT IMPEDANCE  
IOH = IOL = 6 mA (mIN.)  
BALANCED PROPAGATION DELAYS  
tPLH = tPHL  
WIDE OPERATING VOLTAGE RANGE  
.
.
.
.
.
.
.
B1R  
M1R  
(Plastic Package)  
(Micro Package)  
ORDER CODES :  
M74HCXXXM1R  
M74HCXXXB1R  
VCC (OPR) = 2 V TO 6 V  
PIN AND FUNCTION COMPATIBLE  
WITH 54/74LS651/652  
PIN CONNECTIONS (top view)  
DESCRIPTION  
M74HC651/652 are high speed CMOS OCTAL  
BUS TRANSCEIVERS AND REGISTERS (3-  
STATE), fabricated in silicon gate C2MOS technol-  
ogy. They have the same high speed performance  
of LSTTL combined with trueCMOS low power con-  
sumption. These devices consist of bus transceiver  
circuits, D-type flip-flops, and control circuitry ar-  
ranged for multiplexed transmission of data directly  
from the input bus or from the internal storage reg-  
isters. Enable GABand GBA are provided to control  
the transceiver functions.  
Select AB and Select BA control pins are provided  
to select whether real-time or stored data is trans-  
fered. A low input level selects real-time data, and  
a high selects stored data.  
Data on the A or B bus, or both, can be stored in the  
internal D flip-flops by low-to-high transitions at the  
appropriate clock pins (CLOCK AB or CLOCK BA)  
regardless oftheselect or enable control pins. When  
select AB and select BA are in the real-time transfer  
mode, it is also possible to store data without using  
the internal D-type flip-flops by simultaneously en-  
abling GAB and GBA. In this configuration each out-  
put reinforces its input. Thus, when all other data  
sources to the two sets of bus lines are at high im-  
pedance, each set of bus lines will remain at its last  
state. All inputs are equipped with protection circuits  
against static discharge and transient excess volt-  
age.  
INPUT AND OUTPUT EQUIVALENT CIRCUIT  
GAB, GAB, CAB,  
SAB, SBA, CBA  
A, B  
October 1993  
1/12  

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