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M74HC643F1 PDF预览

M74HC643F1

更新时间: 2024-11-29 13:10:11
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意法半导体 - STMICROELECTRONICS 总线收发器
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M74HC643F1 数据手册

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M54/74HC245/640/643  
M54/74HC245/640/643  
OCTAL BUS TRANSCEIVER (3-STATE): HC245 NON INVERTING  
HC640 INVERTING, HC643 INVERTING/NON INVERTING  
.
HIGH SPEED  
PD = 10 ns (TYP.) at VCC = 5V  
LOW POWER DISSIPATION  
ICC = 4 µA (MAX.) at TA = 25 oC  
HIGH NOISE IMMUNITY  
t
.
.
.
.
.
.
.
V
NIH = VINL = 28 % VCC (MIN.)  
OUTPUT DRIVE CAPABILITY  
15 LSTTL LOADS  
SYMMETRICAL OUTPUT IMPEDANCE  
|IOH| = IOL = 6 mA (MIN)  
BALANCED PROPAGATION DELAYS  
tPLH = tPHL  
WIDE OPERATING VOLTAGE RANGE  
VCC (OPR) = 2 V TO 6 V  
B1R  
F1R  
(Plastic Package)  
(Ceramic Package)  
M1R  
C1R  
(Micro Package)  
(Chip Carrier)  
PIN AND FUNCTION COMPATIBLE  
WITH 54/74LS245/640/643  
ORDER CODES :  
M54HCXXXF1R  
M74HCXXXM1R  
M74HCXXXB1R  
M74HCXXXC1R  
DESCRIPTION  
The M54/74HC245, HC640 and HC643 utilise  
silicon gate C2MOS technology to achive operating  
speeds equivalent to LSTTL devices.  
All input are equipped with protection circuits  
against staticdischarge and transient discharge and  
transient excess voltage.  
Along with the low power dissipation and high noise  
immunity of standards C2MOS integrated circuit, it  
possesses the capability to drive 15 LSTTL loads.  
These IC’s are intended for two-way asynchronous  
communication between data buses, and the  
direction of data trasmission is determined by DIR  
input. The enable input (G) can be used to disable  
the device so that the buses are effectively isolated.  
IT IS PROHIBITED TO APPLY A SIGNAL TO A  
BUS TERMINAL WHEN IT IS IN OUTPUT MODE  
AND WHEN A BUS THERMINAL IS FLOATING  
(HIGH IMPEDANCE STATE), IT IS REQUESTED  
TO FIX THE INPUT LEVEL BY MEANS OF  
EXTERNAL PULL DOWN OR PULL UP  
RESISTOR.  
PIN CONNECTION (top view)  
HC245  
HC640  
HC643  
October 1993  
1/11  

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