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M74HC640TTR PDF预览

M74HC640TTR

更新时间: 2024-11-29 05:00:51
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 总线收发器输出元件
页数 文件大小 规格书
11页 307K
描述
OCTAL BUS TRANSCEIVER WITH 3 STATE OUTPUTS (INVERTING)

M74HC640TTR 技术参数

生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP, TSSOP20,.25针数:20
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.43控制类型:COMMON CONTROL
计数方向:BIDIRECTIONAL系列:HC/UH
JESD-30 代码:R-PDSO-G20长度:6.5 mm
逻辑集成电路类型:BUS TRANSCEIVER最大I(ol):0.006 A
位数:8功能数量:1
端口数量:2端子数量:20
最高工作温度:125 °C最低工作温度:-55 °C
输出特性:3-STATE输出极性:INVERTED
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP20,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法:TAPE AND REEL
电源:2/6 VProp。Delay @ Nom-Sup:27 ns
传播延迟(tpd):180 ns认证状态:Not Qualified
座面最大高度:1.2 mm子类别:Bus Driver/Transceivers
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):4.5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL翻译:N/A
宽度:4.4 mmBase Number Matches:1

M74HC640TTR 数据手册

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M74HC640  
OCTAL BUS TRANSCEIVER  
WITH 3 STATE OUTPUTS (INVERTING)  
HIGH SPEED:  
= 10ns (TYP.) at V = 6V  
t
PD  
CC  
LOW POWER DISSIPATION:  
= 4µA(MAX.) at T =25°C  
I
CC  
A
HIGH NOISE IMMUNITY:  
= V = 28 % V (MIN.)  
V
NIH  
NIL  
CC  
DIP  
SOP  
TSSOP  
T & R  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 6mA (MIN)  
OH  
OL  
BALANCED PROPAGATION DELAYS:  
t
t
ORDER CODES  
PACKAGE  
PLH  
PHL  
WIDE OPERATING VOLTAGE RANGE:  
(OPR) = 2V to 6V  
TUBE  
V
CC  
DIP  
SOP  
M74HC640B1R  
M74HC640M1R  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 640  
M74HC640RM13TR  
M74HC640TTR  
TSSOP  
DESCRIPTION  
The 74HC640 is an advanced high-speed CMOS  
DIR input. The enable input G can be used to  
disable the device so that the buses are effectively  
isolated.  
All inputs are equipped with protection circuits  
against static discharge and transient excess  
voltage.  
OCTAL  
BUS  
TRANSCEIVER  
(3-STATE)  
2
fabricated with silicon gate C MOS technology.  
This IC is intended for two-way asynchronous  
communication between data buses, and the  
direction of data transmission is determined by  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
August 2001  
1/11  

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