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M65KA512AB83 PDF预览

M65KA512AB83

更新时间: 2024-11-24 08:16:47
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 动态存储器
页数 文件大小 规格书
55页 473K
描述
IC,SDRAM,4X8MX16,CMOS,DIE

M65KA512AB83 数据手册

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M65KA512AB  
512Mbit (4 Banks x 8M x 16), 133MHz Clock Rate,  
Bare Die, 1.8V Supply, Low Power SDRAM  
Features summary  
512Mbit Synchronous Dynamic Ram  
– Organized as 4 Banks of 8MWords, each  
16 bits wide  
Supply Voltage  
– VDD = 1.7 to 1.9V (1.8V typical in  
accordance with JEDEC standard)  
– VDDQ = 1.7 to 1.9V for Input/Output  
Synchronous Burst Read and Write  
– Fixed Burst Lengths: 1, 2, 4, 8 Words or  
Full Page  
– Burst Types: Sequential and Interleaved.  
– Clock Frequency: 133MHz (7.5ns speed  
class)  
Wafer  
– Clock Valid to Output Delay (CAS Latency):  
3 at 133MHz  
– Burst Control by Burst Stop and Precharge  
Command  
Automatic and controlled Precharge  
Byte control by LDQM and UDQM  
Low-power features:  
– Partial Array Self Refresh (PASR),  
– Automatic Temperature Compensated Self  
Refresh (TCSR)  
– Driver Strength (DS)  
– Deep Power-Down Mode  
Auto Refresh and Self Refresh  
LVCMOS Interface compatible with  
multiplexed addressing  
Operating temperature range  
25 to 85°C  
M65KA512AB IS ONLY AVAILABLE AS PART OF A MULTIPLE MEMORY PRODUCT  
Rev1.0  
1/55  
January 2006  
www.st.com  
1

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