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M65KG256AB8W8 PDF预览

M65KG256AB8W8

更新时间: 2024-11-23 03:04:07
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 存储内存集成电路动态存储器双倍数据速率时钟
页数 文件大小 规格书
51页 508K
描述
256Mbit (4 Banks x 4M x 16) 1.8V Supply, 133MHz Clock Rate, DDR Low Power SDRAM

M65KG256AB8W8 技术参数

生命周期:Obsolete零件包装代码:WAFER
包装说明:DIE, WAFERReach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.32.00.24
风险等级:5.84Is Samacsys:N
访问模式:FOUR BANK PAGE BURST最长访问时间:6 ns
其他特性:AUTO/SELF REFRESH最大时钟频率 (fCLK):133 MHz
I/O 类型:COMMON交错的突发长度:2,4,8,16
JESD-30 代码:X-XUUC-N内存密度:268435456 bit
内存集成电路类型:DDR DRAM内存宽度:16
功能数量:1端口数量:1
字数:16777216 words字数代码:16000000
工作模式:SYNCHRONOUS最高工作温度:85 °C
最低工作温度:-30 °C组织:16MX16
输出特性:3-STATE封装主体材料:UNSPECIFIED
封装代码:DIE封装等效代码:WAFER
封装形状:UNSPECIFIED封装形式:UNCASED CHIP
电源:1.8 V认证状态:Not Qualified
刷新周期:8192自我刷新:YES
连续突发长度:2,4,8,16最大待机电流:0.00001 A
子类别:DRAMs最大压摆率:0.13 mA
最大供电电压 (Vsup):1.9 V最小供电电压 (Vsup):1.7 V
标称供电电压 (Vsup):1.8 V表面贴装:YES
技术:CMOS温度等级:OTHER
端子形式:NO LEAD端子位置:UPPER
Base Number Matches:1

M65KG256AB8W8 数据手册

 浏览型号M65KG256AB8W8的Datasheet PDF文件第2页浏览型号M65KG256AB8W8的Datasheet PDF文件第3页浏览型号M65KG256AB8W8的Datasheet PDF文件第4页浏览型号M65KG256AB8W8的Datasheet PDF文件第5页浏览型号M65KG256AB8W8的Datasheet PDF文件第6页浏览型号M65KG256AB8W8的Datasheet PDF文件第7页 
M65KG256AB  
256Mbit (4 Banks x 4M x 16)  
1.8V Supply, 133MHz Clock Rate, DDR Low Power SDRAM  
PRELIMINARY DATA  
Features summary  
256Mbit SYNCHRONOUS DYNAMIC RAM  
– Organized as 4 Banks of 4MWords, each  
16 bits wide  
DOUBLE DATA RATE (DDR)  
– 2 Data Transfers/Clock Cycle  
– Data Rate: 266Mbit/s (max.)  
SUPPLY VOLTAGE  
– VDD = 1.7 to 1.9V (1.8V typical in  
accordance with JEDEC standard)  
– VDDQ = 1.7 to 1.9V for Inputs/Outputs  
SYNCHRONOUS BURST READ AND WRITE  
– Fixed Burst Lengths: 2, 4, 8, 16 Words  
– Burst Types: Sequential and Interleaved.  
Wafer  
– Clock Frequency: 133MHz (7.5ns speed  
class)  
– Clock Valid to Output Delay (CAS Latency):  
3 at 133MHz  
– Burst Read Control by Burst Read  
Terminate and Precharge Commands  
AUTOMATIC PRECHARGE  
BYTE WRITE CONTROLLED BY LDQM AND  
UDQM  
LOW-POWER FEATURES:  
– Partial Array Self Refresh (PASR)  
– Automatic Temperature Compensated Self  
Refresh (ATCSR)  
– Driver Strength (DS)  
– Deep Power-Down Mode  
– Auto Refresh and Self Refresh  
LVCMOS Interface Compatible with  
Multiplexed Addressing  
OPERATING TEMPERATURE  
– - 30 to 85°C  
The M65KG256AB is only available as part of a multi-chip package Product.  
February 2006  
Rev 1.0  
1/51  
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to  
change without notice.  
www.st.com  
1

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