Datasheet > M65KG256AB

M65KG256AB

更新时间： 2024-11-26 03:04:07

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		动态存储器双倍数据速率时钟
页数	文件大小	规格书
51页	508K
描述
256Mbit (4 Banks x 4M x 16) 1.8V Supply, 133MHz Clock Rate, DDR Low Power SDRAM

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M65KG256AB 数据手册

M65KG256AB

256Mbit (4 Banks x 4M x 16)

1.8V Supply, 133MHz Clock Rate, DDR Low Power SDRAM

PRELIMINARY DATA

Features summary

■ 256Mbit SYNCHRONOUS DYNAMIC RAM

– Organized as 4 Banks of 4MWords, each

16 bits wide

■ DOUBLE DATA RATE (DDR)

– 2 Data Transfers/Clock Cycle

– Data Rate: 266Mbit/s (max.)

■ SUPPLY VOLTAGE

– V_DD= 1.7 to 1.9V (1.8V typical in

accordance with JEDEC standard)

– V_DDQ= 1.7 to 1.9V for Inputs/Outputs

■ SYNCHRONOUS BURST READ AND WRITE

– Fixed Burst Lengths: 2, 4, 8, 16 Words

– Burst Types: Sequential and Interleaved.

Wafer

– Clock Frequency: 133MHz (7.5ns speed

class)

– Clock Valid to Output Delay (CAS Latency):

3 at 133MHz

– Burst Read Control by Burst Read

Terminate and Precharge Commands

■ AUTOMATIC PRECHARGE

■ BYTE WRITE CONTROLLED BY LDQM AND

UDQM

■ LOW-POWER FEATURES:

– Partial Array Self Refresh (PASR)

– Automatic Temperature Compensated Self

Refresh (ATCSR)

– Driver Strength (DS)

– Deep Power-Down Mode

– Auto Refresh and Self Refresh

■ LVCMOS Interface Compatible with

Multiplexed Addressing

■ OPERATING TEMPERATURE

– - 30 to 85°C

The M65KG256AB is only available as part of a multi-chip package Product.

February 2006

Rev 1.0

1/51

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to

change without notice.

www.st.com

12 3 4 5 6 7...51

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