Datasheet > M5M5V2132GP-5H

M5M5V2132GP-5H

更新时间： 2024-11-21 19:22:55

品牌	Logo	应用领域
三菱 - MITSUBISHI		时钟静态存储器内存集成电路
页数	文件大小	规格书
14页	167K
描述
Cache SRAM, 64KX32, 5ns, CMOS, PQFP100, 14 X 20 MM, 0.65 MM PITCH, PLASTIC, TQFP-100

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M5M5V2132GP-5H 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	QFP	包装说明：	QFP, QFP100(UNSPEC)
针数：	100	Reach Compliance Code：	unknown
ECCN代码：	3A991.B.2.A	HTS代码：	8542.32.00.41
风险等级：	5.85	最长访问时间：	5 ns
最大时钟频率 (fCLK)：	133 MHz	I/O 类型：	COMMON
JESD-30 代码：	R-PQFP-G100	JESD-609代码：	e0
内存密度：	2097152 bit	内存集成电路类型：	CACHE SRAM
内存宽度：	32	功能数量：	1
端子数量：	100	字数：	65536 words
字数代码：	64000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	64KX32	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	QFP
封装等效代码：	QFP100(UNSPEC)	封装形状：	RECTANGULAR
封装形式：	FLATPACK	并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	NOT SPECIFIED	电源：	3.3 V
认证状态：	Not Qualified	最大待机电流：	0.002 A
最小待机电流：	3.14 V	子类别：	SRAMs
最大压摆率：	0.3 mA	最大供电电压 (Vsup)：	3.47 V
最小供电电压 (Vsup)：	3.13 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING	端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED	Base Number Matches：	1

M5M5V2132GP-5H 数据手册

Mar.24.'97 ver.G

M5M5V2132GP-5^MH^IT,-^S5^U,^B-^I6^SH,-^I7^L,^S-^I8^s

2097152-BIT(65536-WORD BY 32-BIT) SYNCHRONOUS BURST SRAM

When CLK is stopped and all inputs (Address, Burst control,

DESCRIPTION

CLK etc. ) are fixed in CMOS level, the SRAM becomes in the

power-down state that is called "CLK stopped stand-by mode".

During CLK stopped stand-by mode, power supply current is

almost same as snooze mode even if the SRAM is selected.

When CLK is active again, the SRAM immediately recovers from

CLK stopped stand-by mode to normal operation mode.

The M5M5V2132 is a family of 2M bit synchronous SRAMs

organized as 65536-words of 32-bit. The M5M5V2132 provides a

high speed secondary cache solution for microprocessors. The

design integrates a 2-bit burst counter, input and output registers

with the ultra fast 2M bit SRAM on a single monolithic circuit. This

design reduces component count of cache data RAM solutions.

Mitsubishi's SRAMs are fabricated with high-performance, low

power Super CMOS technology, providing greater reliability. This

device operates on 3.3V power / 2.5V I/O supply or a single 3.3V

power supply , and are directly LVTTL compatible.

The burst mode control (MODE), and the flow-through enable

(FT) are DC operated pins. MODE pin will allow the choice of

either an interleaved burst, or a linear burst. FT pin normally is

VDD. When FT is pulled Vss, the SRAM changes non-pipelined

type with flow-through output. FT input fixed to Vss is only used

for a test mode.

FEATURES

Access times / Cycle times

The burst operation is initiated by either address status

processor (ADSP) or address status controller (ADSC). The burst

advance pin (ADV) controls subsequent burst addresses.

......................

5.0ns/7.5ns (133MHz)

5.0ns/8.5ns (117MHz)

5.5ns/10.0ns(100MHz)

7.0ns/13.3ns (75MHz)

8.0ns/15.0ns (66MHz)

M5M5V2132GP-5H

M5M5V2132GP-5

M5M5V2132GP-6

M5M5V2132GP-7

M5M5V2132GP-8

.....................

...........................

875mW (typ)

3.3mW (typ)

Low power dissipation

Active(133MHz)

Stand-by

.......

-5H,-5,-6

3.3V(3.13V ~ 3.47V )power

/ 2.5V(2.37V ~ 2.90V) I/O supply

or Single 3.3V(3.13V ~ 3.47V )power supply

3.3V(3.13V ~ 3.60V )power

.......

-7 ,-8

/ 2.5V(2.37V ~ 2.90V) I/O supply

or Single 3.3V(3.13V ~ 3.60V )power supp

Package

100pin TQFP

Body Size (14.0 x 20.0 mm ) Pin Pitch (0.65 mm)

Fully registered inputs and outputs (Pipeline operation)

Global write control or individual byte write control

MODE pin allows either liner or interleaved burst

Snooze mode pin (ZZ) for power down

CLK stopped stand-by mode

32-bit wide data I/O

APPLICATION

Pentium^TM/ PowerPC^TMand High-end processor second level

caches

FUNCTION

Synchronous circuitry allows for precise cycle control triggered by

a positive edge clock transition. Synchronous signals include : all

addresses, all data inputs, all chip selects (S1, S2, S2), burst

control inputs (ADSC, ADSP, ADV) and write enables (MBW, GW,

BW1, BW2, BW3, BW4). S2 and S2 provide easy depth expansion.

The write operation can be performed by two methods. The

global write enable (GW) will perform a write to all 32 bits. Byte

wide writes are controlled by the master byte write enable (MBW)

and the 4 individual byte write enables (BW1-BW4). The byte write

cycle will write from one to four bytes. The write cycle is internally

self-timed, eliminating the complex signal generation of an off chip

write.

Asynchronous signals are output enable (OE), snooze mode pin

(ZZ) and clock (CLK). The HIGH input of ZZ pin puts the SRAM in

the power-down state. When ZZ is pulled to LOW, the SRAM

normally operates after 30ns of the wake up period.

12 3 4 5 6 7...14

中文翻译

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与M5M5V2132GP-5H相关器件

型号	品牌	获取价格	描述	数据表
M5M5V216ART	MITSUBISHI	获取价格	2097152-BIT (131072-WORD BY 16-BIT) CMOS STATIC RAM
M5M5V216ART	RENESAS	获取价格	2097152-BIT (131072-WORD BY 16-BIT) CMOS STATIC RAM
M5M5V216ART-55HI	RENESAS	获取价格	2097152-BIT (131072-WORD BY 16-BIT) CMOS STATIC RAM
M5M5V216ART-55HI	MITSUBISHI	获取价格	Standard SRAM, 128KX16, 55ns, CMOS, PDSO44, 0.400 INCH, REVERSE, TSOP2-44
M5M5V216ART-55HW	MITSUBISHI	获取价格	Standard SRAM, 128KX16, 55ns, CMOS, PDSO44, 0.400 INCH, REVERSE, TSOP2-44
M5M5V216ART-55LW	MITSUBISHI	获取价格	Standard SRAM, 128KX16, 55ns, CMOS, PDSO44, 0.400 INCH, REVERSE, TSOP2-44
M5M5V216ART-70HI	RENESAS	获取价格	2097152-BIT (131072-WORD BY 16-BIT) CMOS STATIC RAM
M5M5V216ART-70HI	MITSUBISHI	获取价格	Standard SRAM, 128KX16, 70ns, CMOS, PDSO44, 0.400 INCH, REVERSE, TSOP2-44
M5M5V216ART-70HW	MITSUBISHI	获取价格	Standard SRAM, 128KX16, 70ns, CMOS, PDSO44, 0.400 INCH, REVERSE, TSOP2-44
M5M5V216ART-70LI	MITSUBISHI	获取价格	Standard SRAM, 128KX16, 70ns, CMOS, PDSO44, 0.400 INCH, REVERSE, TSOP2-44

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