(Rev. 1.0)
MITSUBISHI LSIs
M5M467400/465400DJ,DTP -5,-6,-5S,-6S
M5M467800/465800DJ,DTP -5,-6,-5S,-6S
M5M465160DJ,DTP -5,-6,-5S,-6S
FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
Some of contents are subject to change without notice.
PRELIMINARY
DESCRIPTION
The M5M467400/465400DJ,DTP is a 16777216-word by 4-bit, M5M467800/465800DJ,DTP is a 8388608-word by 8-bit, and
M5M465160DJ,DTP is a 4194304-word by 16-bit dynamic RAMs, fabricated with the high performance CMOS process, and are
suitable for large-capacity memory systems with high speed and low power dissipation.
FEATURES
Address
access access access
time time time
Power
dissipa-
tion
RAS
OE
Power
dissipa-
tion
CAS
Cycle
time
Address
access
time
RAS
access access
time time
CAS
OE
Cycle
time
access
time
access
time
Type name
Type name
(max.ns) (max.ns) (max.ns) (max.ns) (min.ns) (typ.mW)
(max.ns) (max.ns) (max.ns) (max.ns)
(min.ns)
(typ.mW)
M5M467400DXX-5,5S
M5M467800DXX-5,5S
M5M465160DXX-5,5S
M5M465160DXX-6,6S
50
60
13
15
420
90
13
15
25
30
50
60
50
60
13
15
13
15
25
30
25
30
13
15
13
15
90
110
90
300
250
390
325
M5M467400DXX-6,6S
M5M467800DXX-6,6S
390
110
M5M465400DXX-5,5S
M5M465800DXX-5,5S
M5M465400DXX-6,6S
M5M465800DXX-6,6S
110
XX=J,TP
(M5M467400Dxx/M5M465400Dxx/M5M467800Dxx/M5M465800Dxx)
(M5M465160Dxx)
Standard 32 pin SOJ, 32 pin TSOP
Standard 50 pin SOJ, 50 pin TSOP
±
Single 3.3 0.3V supply
Low stand-by power dissipation
1.8mW (Max)
LVCMOS input level
Low operating power dissipation
M5M467400Dxx-5,5S / M5M467800Dxx-5,5S
M5M467400Dxx-6,6S / M5M467800Dxx-6,6S
M5M465400Dxx-5,5S / M5M465800Dxx-5,5S
M5M465400Dxx-6,6S / M5M465800Dxx-6,6S
M5M465160Dxx-5,5S
360.0mW (Max)
324.0mW (Max)
468.0mW (Max)
432.0mW (Max)
504.0mW (Max)
468.0mW (Max)
M5M465160Dxx-6,6S
Self refresh capability*
Self refresh current
400µA (Max)
Fast-page mode , Read-modify-write, CAS before RAS refresh, Hidden refresh capabilities
Early-write mode and OE to control output buffer impedance
All inputs, outputs LVTTL compatible and low capacitance
:Applicable to self refresh version(M5M467400/465400/467800/465800/465160DJ,DTP-5S,-6S:option) only
*
ADDRESS
Refresh Cycle
Normal S-version
8192/64ms 8192/128ms
Row Add. Col. Add.
Refresh
Part No.
RAS Only Ref,Normal R/W
CBR Ref,Hidden Ref
M5M467400Dxx A0-A12 A0-A10
4096/64ms
4096/64ms
4096/128ms
4096/128ms
RAS Only Ref,Normal R/W
CBR Ref,Hidden Ref
M5M465400Dxx
A0-A11 A0-A11
8192/64ms 8192/128ms
RAS Only Ref,Normal R/W
CBR Ref,Hidden Ref
M5M467800Dxx A0-A12 A0-A9
4096/64ms
4096/64ms
4096/128ms
4096/128ms
RAS Only Ref,Normal R/W
CBR Ref,Hidden Ref
M5M465800Dxx
M5M465160Dxx
A0-A10
A0-A9
A0-A11
A0-A11
RAS Only Ref,Normal R/W
CBR Ref,Hidden Ref
4096/128ms
4096/64ms
APPLICATION
Main memory unit for computers, Microcomputer memory, Refresh memory for CRT
Aug. 1999
1
MITSUBISHI ELECTRIC