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M5M44265CTP-7T PDF预览

M5M44265CTP-7T

更新时间: 2024-11-09 13:10:07
品牌 Logo 应用领域
三菱 - MITSUBISHI 存储内存集成电路光电二极管动态存储器
页数 文件大小 规格书
31页 321K
描述
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M5M44265CTP-7T 数据手册

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MITSUBISHI LSIs  
M5M44265CJ,TP-5,-6,-7,
-5S,-6S,-7S  
EDO (HYPER PAGE MODE) 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM  
DESCRIPTION  
PIN CONFIGURATION (TOP VIEW)  
This is a family of 262144-word by 16-bit dynamic RAMs with  
Hyper Page mode fuction, fabricated with the high performance  
CMOS process, and is ideal for the buffer memory systems of  
personal computer graphics and HDD where high speed, low  
power dissipation, and low costs are essential.  
The use of double-layer metalization process technology and a  
single-transistor dynamic storage stacked capacitor cell provide  
high circuit density at reduced costs. Multiplexed address inputs  
permit both a reduction in pins and an increase in system  
densities. Self or extended refresh current is low enough for  
battery back-up application.  
VSS(0V)  
(5V)VCC  
DQ1  
40  
39  
38  
1
2
DQ16  
DQ15  
DQ2  
3
4
5
DQ3  
DQ4  
37 DQ14  
36  
35 VSS(0V)  
DQ13  
(5V)VCC  
DQ5  
6
7
34  
33  
32  
DQ12  
DQ11  
DQ10  
This device has 2CAS and 1W terminals with a refresh cycle of  
512 cycles every 8.2ms.  
DQ6  
8
DQ7  
9
31 DQ9  
30 NC  
DQ8  
10  
11  
FEATURES  
NC  
Power  
dissipa-  
tion  
OE  
access  
time  
RAS  
access access  
time time  
CAS  
Address  
access  
time  
Cycle  
time  
(min.ns)  
NC  
29  
LCAS  
12  
13  
14  
Type name  
(typ.mW)  
(max.ns) (max.ns) (max.ns) (max.ns)  
28  
W
RAS  
NC  
UCAS  
M5M44265CXX-5,-5S  
M5M44265CXX-6,-6S  
M5M44265CXX-7,-7S  
XX=J,TP  
50  
60  
70  
13  
15  
20  
25  
30  
35  
13  
15  
20  
90  
110  
130  
625  
550  
475  
27  
OE  
15  
16  
26  
25  
24  
23  
22  
A8  
A7  
A6  
A5  
A4  
A0  
17  
18  
A1  
A2  
Standard 40pin SOJ, 44 pin TSOP (II)  
Single 5V±10% supply  
Low stand-by power dissipation  
CMOS Input level  
19  
20  
A3  
5.5mW (Max)  
550µW (Max)*  
21 VSS(0V)  
(5V)VCC  
CMOS Input level  
Operating power dissipation  
M5M44265Cxx-5,-5S  
688mW (Max)  
605mW (Max)  
523mW (Max)  
Outline 40P0K (400mil SOJ)  
M5M44265Cxx-6,-6S  
M5M44265Cxx-7,-7S  
Self refresh capability*  
Self refresh current  
Extended refresh capability  
Extended refresh current  
Hyper-page mode (512-column random access), Read-modify-  
write, RAS-only refresh, CAS before RAS refresh, Hidden refresh  
capabilities.  
Early-write mode, OE and W to control output buffer impedance  
512 refresh cycles every 8.2ms (A0~A8)  
(5V)VCC  
1
2
44 VSS(0V)  
150µA (Max)  
150µA (Max)  
43  
DQ1  
DQ2  
DQ16  
42  
3
4
DQ15  
41  
40  
39  
DQ14  
DQ13  
DQ3  
DQ4  
5
6
(5V)VCC  
DQ5  
VSS(0V)  
DQ12  
512 refresh cycles every 128ms (A0~A8)*  
Byte or word control for Read/Write operation (2CAS, 1W type)  
7
8
9
38  
DQ11  
DQ10  
DQ9  
DQ6  
37  
36  
* : Applicable to self refresh version (M5M44265CJ,TP-5S,-6S,-7S  
: option) only  
DQ7  
DQ8 10  
35  
APPLICATION  
Microcomputer memory, Refresh memory for CRT, Frame Buffer  
memory for CRT  
NC  
13  
32  
31  
30  
NC  
14  
15  
16  
17  
18  
19  
20  
21  
22  
NC  
W
LCAS  
PIN DESCRIPTION  
UCAS  
OE  
Pin name  
A0~A8  
Function  
Address inputs  
29  
28  
RAS  
NC  
A0  
A8  
Data inputs / outputs  
DQ1~DQ16  
RAS  
27 A7  
Row address strobe input  
26  
25  
24  
23  
A6  
A1  
A2  
Lower byte control  
LCAS  
UCAS  
A5  
A4  
column address strobe input  
Upper byte control  
column address strobe input  
A3  
VSS(0V)  
(5V)VCC  
Write control input  
W
Output enable input  
Power supply (+5V)  
Ground (0V)  
OE  
VCC  
VSS  
Outline 44P3W-R (400mil TSOP Nomal Bend)  
NC: NO CONNECTION  
1

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