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M5M416100CJ-6 PDF预览

M5M416100CJ-6

更新时间： 2024-01-29 23:20:10
品牌 Logo 应用领域
三菱 - MITSUBISHI 动态存储器光电二极管内存集成电路
页数 文件大小 规格书
21页 173K
描述
Fast Page DRAM, 16MX1, 60ns, CMOS, PDSO24, 0.300 INCH, SOJ-26/24

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M5M416100CJ-6 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：SOJ包装说明：SOJ, SOJ24/26,.34
针数：24Reach Compliance Code：unknown
ECCN代码：EAR99HTS代码：8542.32.00.02
风险等级：5.91访问模式：FAST PAGE
最长访问时间：60 ns其他特性：RAS ONLY/CAS BEFORE RAS/HIDDEN/SELF REFRESH
I/O 类型：SEPARATEJESD-30 代码：R-PDSO-J24
JESD-609代码：e0长度：17.14 mm
内存密度：16777216 bit内存集成电路类型：FAST PAGE DRAM
内存宽度：1功能数量：1
端口数量：1端子数量：24
字数：16777216 words字数代码：16000000
工作模式：ASYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：16MX1
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：SOJ封装等效代码：SOJ24/26,.34
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
峰值回流温度（摄氏度）：NOT SPECIFIED电源：5 V
认证状态：Not Qualified刷新周期：4096
座面最大高度：3.55 mm自我刷新：YES
最大待机电流：0.0005 A子类别：DRAMs
最大压摆率：0.09 mA最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：J BEND端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：7.62 mm

M5M416100CJ-6 数据手册

 浏览型号M5M416100CJ-6的Datasheet PDF文件第1页浏览型号M5M416100CJ-6的Datasheet PDF文件第2页浏览型号M5M416100CJ-6的Datasheet PDF文件第3页浏览型号M5M416100CJ-6的Datasheet PDF文件第5页浏览型号M5M416100CJ-6的Datasheet PDF文件第6页浏览型号M5M416100CJ-6的Datasheet PDF文件第7页 
MITSUBISHI LSIs  
M5M416100C J,TP -5, -6, -7, -5S, -6S, -7S  
FAST PAGE MODE 16777216-BIT ( 16777216-WORD BY 1-BIT ) DYNAMIC RAM  
(Ta=0 ~70°C, Vcc=5V±10%, Vss=0V, unless otherwise noted , see notes 5,12,13)  
SWITCHING CHARACTERISTICS  
Limits  
M5M416100C-5,-5S M5M416100C-6,-6S M5M416100C-7,-7S  
Symbol  
Parameter  
Unit  
Min  
Max  
13  
Min  
Max  
15  
Min  
Max  
20  
ns  
ns  
ns  
ns  
ns  
ns  
Access time from CAS  
tCAC  
tRAC  
tAA  
(Note 6,7)  
(Note 6,8)  
(Note 6,9)  
(Note 6,10)  
50  
60  
70  
Access time from RAS  
Column address access time  
Access time from CAS precharge  
25  
30  
35  
30  
35  
40  
tCPA  
tCLZ  
tOFF  
5
0
5
0
5
0
Output low impedance time from CAS low (Note 6)  
Output disable time after CAS high (Note 11)  
13  
15  
15  
Note 5: An initial pause of 500µs is required after power-up followed by a minimum of eight initialization RAS cycles. The initialization cycles  
should be done either by RAS-Only refresh cycles or by CAS-before-RAS refresh cycles only.  
Note the RAS may be cycled during the initial pause . And any 8 RAS or RAS/CAS cycles are required after prolonged periods  
(greater than 64 ms) of RAS inactivity before proper device operation is achieved.  
After the initialization cycles, RAS should be kept either higher than VIHmin or lower than VILmax except RAS transition time.  
6: Measured with a load circuit equivalent to 2TTL loads and 100pF.  
>
>
tASC(max).  
7: Assumes that tRCD  
tRCD(max) and tASC  
=
=
<
<
8: Assumes that tRCD tRCD(max) and tRAD tRAD(max). If tRCD or tRAD is greater than the maximum recommended value shown in this table,  
=
=
tRAC will increase by amount that tRCD exceeds the value shown.  
>
<
9: Assumes that tRAD  
tRAD(max) and tASC tASC(max).  
=
=
<
>
10: Assumes that tCP tCP(max) and tASC tASC(max).  
11: tOFF(max) defines the time at which the output achieves the high impedance state ( IOUT I±10 µAI) and is not reference to  
=
=
<
=
VOH(min) or VOL(max).  
TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write ,Refresh, and Fast-Page Mode Cycles)  
(Ta=0 ~70°C, Vcc=5V±10%, Vss=0V, unless otherwise noted See notes 12,13)  
Limits  
M5M416100C-5,-5S M5M416100C-6,-6S M5M416100C-7,-7S  
Symbol  
Parameter  
Unit  
Min  
Max  
64  
Min  
Max  
64  
Min  
Max  
64  
Refresh cycle time  
tREF  
tRP  
ms  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
RAS high pulse width  
30  
18  
10  
0
40  
20  
10  
0
50  
20  
10  
0
tRCD  
tCRP  
tRPC  
tCPN  
tRAD  
tASR  
tASC  
tRAH  
tCAH  
tT  
(Note14)  
Delay time, RAS low to CAS low  
37  
45  
50  
Delay time, CAS high to RAS low  
Delay time, RAS high to CAS low  
CAS high pulse width  
10  
13  
0
10  
15  
0
10  
15  
0
Column address delay time from RAS low  
(Note15)  
(Note16)  
25  
7
30  
10  
35  
10  
Row address setup time before RAS low  
Column address setup time before CAS low  
0
0
0
Row address hold time after RAS low  
Column address hold time after CAS low  
Transition time  
8
10  
15  
1
10  
15  
1
13  
1
(Note17)  
50  
50  
50  
Note 12: The timing requirements are assumed tT =5ns.  
13: VIH(min) and VIL(max) are reference levels for measuring timing of input signals.  
14: tRCD(max) is specified as a reference point only. If tRCD is less than tRCD(max), access time is tRAC. If tRCD is greater than tRCD(max), access  
time is controlled exclusively by tCAC or tAA. tRCD(min) is specified as tRCD(min) =tRAH(min) +2tH+tASC(min).  
>
<
15: tRAD(max) is specified as a reference point only. If tRAD tRAD(max) and tASC tASC(max), access time is controlled exclusively by tAA.  
=
=
>
>
16: tASC(max) is specified as a reference point only. If tRCD tRCD(max) and tASC tASC(max), access time is controlled exclusively by tCAC.  
=
=
17: tT is measured between VIH(min) and VIL(max).  
Challenging to LowCost &  
HighPerformance  
MITSUBISHI  
ELECTRIC  
4
DRAM  
DRAM  
Oct. 1997  
1234567...21

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