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M59DR032EB10ZB1E PDF预览

M59DR032EB10ZB1E

更新时间: 2024-11-14 10:38:23
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS /
页数 文件大小 规格书
43页 739K
描述
Flash, 2MX16, 100ns, PBGA48, 7 X 12 MM, 0.75 MM PITCH, TFBGA-48

M59DR032EB10ZB1E 数据手册

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M59DR032EA  
M59DR032EB  
32 Mbit (2Mb x 16, Dual Bank, Page )  
1.8V Supply Flash Memory  
FEATURES SUMMARY  
SUPPLY VOLTAGE  
Figure 1. Packages  
– V  
= V  
= 1.65V to 2.2V for Program,  
DDQ  
DD  
Erase and Read  
– V = 12V for fast Program (optional)  
PP  
ASYNCHRONOUS PAGE MODE READ  
– Page Width: 4 Words  
BGA  
– Page Access: 35ns  
– Random Access: 85ns, 100ns and 120ns  
PROGRAMMING TIME  
TFBGA48 (ZB)  
7 x 12mm  
– 10µs by Word typical  
– Double Word Program Option  
MEMORY BLOCKS  
– Dual Bank Memory Array: 4 Mbit, 28 Mbit  
– Parameter Blocks (Top or Bottom location)  
DUAL BANK OPERATIONS  
BGA  
– Read within one Bank while Program or  
Erase within the other  
TFBGA48 (ZF)  
7 x 7mm  
– No delay between Read and Write operations  
BLOCK LOCKING  
– All blocks locked at Power up  
– Any combination of blocks can be locked  
– WP for Block Lock-Down  
COMMON FLASH INTERFACE (CFI)  
– 64 bit Unique Device Identifier  
– 64 bit User Programmable OTP Cells  
ERASE SUSPEND and RESUME MODES  
100,000 PROGRAM/ERASE CYCLES per  
BLOCK  
20 YEARS DATA RETENTION  
– Defectivity below 1ppm/year  
ELECTRONIC SIGNATURE  
– Manufacturer Code: 0020h  
– Top Device Code, M59DR032EA: 00A0h  
– Bottom Device Code, M59DR032EB: 00A1h  
April 2003  
1/43  

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