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M59BW102 PDF预览

M59BW102

更新时间: 2024-09-24 22:25:47
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 闪存
页数 文件大小 规格书
24页 182K
描述
1 Mbit 64Kb x16, Burst Low Voltage Flash Memory

M59BW102 数据手册

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M59BW102  
1 Mbit (64Kb x16, Burst) Low Voltage Flash Memory  
PRELIMINARY DATA  
2.7 to 3.6V SUPPLY VOLTAGE for PROGRAM,  
ERASE and READ OPERATIONS  
SEQUENTIAL CYCLE TIME: 25ns  
RANDOM ACCESS TIME  
PROGRAMMING TIME: 10µs typical  
INTERLEAVED ACCESS TIME: 16ns  
CONTINUOUS MEMORY INTERLEAVING  
– Unlimited Linear Access Data Output  
PROGRAM/ERASE CONTROLLER (P/E.C.)  
TSOP40 (N)  
10 x 14mm  
– Program Word-by-Word  
– Status Register bits  
LOW POWER CONSUMPTION  
– Stand-by and Automatic Stand-by  
100,000 PROGRAM/ERASE CYCLES  
20 YEARS DATA RETENTION  
Figure 1. Logic Diagram  
– Defectivity below 1ppm/year  
ELECTRONIC SIGNATURE  
– Manufacturer Code: 20h  
– Device Code: C1h  
V
CC  
DESCRIPTION  
The M59BW102 is a non-volatile memory that may  
be erased electrically at the chip level and pro-  
grammed in-system on a Word-by-Word basis us-  
16  
16  
ing only a single 3V V supply. For Program and  
CC  
A0-A15  
DQ0-DQ15  
Erase operations the necessary high voltages are  
generated internally. The device can also be pro-  
grammed in standard programmers.  
The device can be programmed and erased over  
100,000 cycles.  
Instructions for Read/Reset, Auto Select for read-  
ing the Electronic Signature, Programming and  
Chip Erase are written to the device in cycles of  
commands to a Command Interface using stan-  
dard microprocessor write timings. The  
M59BW102 features an interleaved access mo-  
dality which allows extremely fast access time.  
The device is offered in TSOP40 (10 x 14mm)  
package.  
W
E
M59BW102  
G
ALE  
V
SS  
AI02763B  
March 2000  
1/24  
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.  

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