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M54HC374DG PDF预览

M54HC374DG

更新时间: 2024-11-06 13:10:07
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 触发器输出元件
页数 文件大小 规格书
11页 288K
描述
Rad-Hard Octal D-Type Flip-Flop 3-State

M54HC374DG 技术参数

生命周期:ActiveReach Compliance Code:compliant
风险等级:5.69Is Samacsys:N
逻辑集成电路类型:D FLIP-FLOPBase Number Matches:1

M54HC374DG 数据手册

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M54HC374  
RAD-HARD OCTAL D-TYPE FLIP FLOP  
WITH 3 STATE OUTPUT NON INVERTING  
HIGH SPEED:  
= 90MHz (TYP.) at V = 6V  
f
MAX  
CC  
LOW POWER DISSIPATION:  
= 4µA(MAX.) at T =25°C  
I
CC  
A
HIGH NOISE IMMUNITY:  
= V = 28% V (MIN.)  
V
NIH  
NIL  
CC  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 6mA (MIN)  
DILC-20  
FPC-20  
OH  
OL  
BALANCED PROPAGATION DELAYS:  
t
t
PLH  
PHL  
ORDER CODES  
PACKAGE  
WIDE OPERATING VOLTAGE RANGE:  
(OPR) = 2V to 6V  
V
FM  
EM  
CC  
PIN AND FUNCTION COMPATIBLE WITH  
54 SERIES 374  
DILC  
FPC  
M54HC374D  
M54HC374K  
M54HC374D1  
M54HC374K1  
SPACE GRADE-1: ESA SCC QUALIFIED  
50 krad QUALIFIED, 100 krad AVAILABLE ON  
REQUEST  
NO SEL UNDER HIGH LET HEAVY IONS  
IRRADIATION  
On the positive transition of the clock, the Q  
outputs will be set to the logic state that were  
setup at the D inputs.  
While the OE input is at low level, the eight outputs  
will be in a normal logic state (high or low logic  
level) and while OE is high the outputs will be in a  
high impedance state.  
DEVICE FULLY COMPLIANT WITH  
SCC-9203-060  
The output control does not affect the internal  
operation of flip-flops; that is, the old data can be  
retained or the new data can be entered even  
while the outputs are off.  
All inputs are equipped with protection circuits  
against static discharge and transient excess  
voltage.  
DESCRIPTION  
The M54HC374 is an high speed CMOS OCTAL  
D-TYPE FLIP FLOP WITH 3-STATE OUTPUTS  
NON INVERTING fabricated with sub-micron  
2
silicon gate C MOS technology.  
This 8 bit D-TYPE FLIP FLOP is controlled by a  
clock input (CK) and an output enable input (OE).  
PIN CONNECTION  
Rev. 1  
1/11  
May 2004  

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